The Era Of Packetized Scan Test Has Arrived


For decades, process and design scaling has triggered the adoption of transformative test solutions. About twenty years ago, when at-speed test became a de-facto requirement, on-chip compression became the norm to address test data time and volume. Over the last decade, hierarchical DFT enabled DFT engineers to apply a divide and conquer on large design, improving both implementation effort and... » read more

High-Quality Test And Embedded Analytics Are Vital For Secure SoCs


Applications such as smart cards and devices used in the defense industry require security features to ensure that sensitive data is inaccessible to outside agents. This used to be a niche requirement met through custom solutions. However, now that automotive and cyber-physical systems are proliferating, the requirements around secure test and monitoring are becoming mainstream. The current bes... » read more

Designing Chips For Test Data


Collecting data to determine the health of a chip throughout its lifecycle is becoming necessary as chips are used in more critical applications, but being able to access that data isn't always so simple. It requires moving signals through a complex, sometimes unpredictable, and often hostile environment, which is a daunting challenge under the best of conditions. There is a growing sense of... » read more

Power-Aware Test: Addressing Power Challenges In DFT And Test


Integrated circuit (IC) sizes continue to grow as they meet the compute requirements of cutting-edge applications such as artificial intelligence (AI), autonomous driving, and data centers. As design sizes increase, the total power consumption of the chip also increases. While process node scaling reduces a transistor’s size and its operating-voltage, power scaling has not kept up with the si... » read more

SLT Enables Test Content To Shift Right


By Dave Armstrong, Davette Berry, and Craig Snyder Increasing device complexity and the continuing drive for higher levels of quality are fostering a reconsideration of test strategies. To be effective, test engineers must choose how to optimally deploy test content, from wafer probing to system-level test (SLT). A March 2019 TestConX presentation1 outlines how test content is typically allo... » read more

MEMS: New Materials, Markets And Packaging


Semiconductor Engineering sat down to talk about future developments and challenges for microelectromechanical systems (MEMS) with Gerold Schropfer, director of MEMS products and European operations in Lam Research's Computational Products group, and Michelle Bourke, senior director of strategic marketing for Lam's Customer Support Business Group. What follows are excerpts of that conversation.... » read more

The Importance Of Product Burn-In Test


Product burn-in (BI) is an indispensable step in the production test flow to ensure good quality and a properly functioning product for the customer. Amkor takes pride in rating ‘quality delivered to the customer’ as one of the highest corporate virtues. See figure 1. Fig. 1: Defects per Million (DPM) and DPM goal reported over five years. Burned-in integrated circuits (ICs) have a ... » read more

Streaming Scan Network


The traditional approach to moving scan test data from chip-level pins to core-level scan channels is under pressure due to the dramatic rise in design size, design complexity, and test adaptation. In the traditional approach to delivering scan test data to cores, each core requires a dedicated connection to chip-level pins, which doesn’t allow for much flexibility, as the dependencies betwee... » read more

Packetized Scan Test Delivery


The traditional approach to moving scan test data from chip-level pins to core-level scan channels is under pressure due to the dramatic rise in design size, design complexity, and test adaptation. To address these challenges, we now have the option of implementing a packetized data network for scan test that moves the scan data through the SoC much more efficiently than the traditional pin-... » read more

Driving Toward Predictive Analytics With Dynamic Parametric Test


The foundation of parametric test within semiconductor manufacturing is its usefulness in determining that wafers have been fabricated properly. Foundries use parametric test results to help verify that wafers can be delivered to a customer. For IDMs, the test determines whether the wafers can be sent on for sorting. Usually inserted into the semiconductor manufacturing flow during wafer fabric... » read more

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