tag: UT Austin

Learning The AMS Circuit Representation From Layout Positions (UT Austin/ NVIDIA)
By Technical Paper Link - 15 Mar, 2023 - Comments: 0

A recent technical paper titled "TAG: Learning Circuit Spatial Embedding From Layouts" was published by researchers at UT Austin and NVIDIA. Abstract "Analog and mixed-signal (AMS) circuit designs still rely on human design expertise. Machine learning has been assisting circuit design automation by replacing human experience with artificial intelligence. This paper presents TAG, a new parad... » read more

Chip Industry’s Technical Paper Roundup: Mar. 6
By Linda Christensen - 06 Mar, 2023 - Comments: 0

New technical papers recently added to Semiconductor Engineering’s library: [table id=84 /] If you have research papers you are trying to promote, we will review them to see if they are a good fit for our global audience. At a minimum, papers need to be well researched and documented, relevant to the semiconductor ecosystem, and free of marketing bias. There is no cost involved for us ... » read more

Microarchitectural Side-Channel Attacks And Defenses On Non-Volatile RAM
By Technical Paper Link - 04 Mar, 2023 - Comments: 0

A new technical paper titled "NVLeak: Off-Chip Side-Channel Attacks via Non-Volatile Memory Systems" was written (preprint) by researchers at UC San Diego, UT Austin, and Purdue University. Abstract "We study microarchitectural side-channel attacks and defenses on non-volatile RAM (NVRAM) DIMMs. In this study, we first perform reverse-engineering of NVRAMs as implemented by the Intel Optane... » read more

Asynchronously Parallel Optimization Method For Sizing Analog Transistors Using Deep Neural Network Learning
By Technical Paper Link - 03 Mar, 2023 - Comments: 0

A new technical paper titled "APOSTLE: Asynchronously Parallel Optimization for Sizing Analog Transistors Using DNN Learning" was published by researchers at UT Austin and Analog Devices. Abstract "Analog circuit sizing is a high-cost process in terms of the manual effort invested and the computation time spent. With rapidly developing technology and high market demand, bringing automated s... » read more

Modeling and Thermal Analysis of 3DIC
By Technical Paper Link - 13 Feb, 2023 - Comments: 0

A new technical paper titled "Heat transfer in a multi-layered semiconductor device with spatially-varying thermal contact resistance between layers" was published by researchers at UT Arlington. "This work presents a theoretical model to determine the steady state temperature distribution in a general M-layer structure with spatial variation in thermal contact resistance between adjacent la... » read more

Chip Industry’s Technical Paper Roundup: Dec. 20
By Linda Christensen - 20 Dec, 2022 - Comments: 0

New technical papers added to Semiconductor Engineering’s library this week. [table id=71 /] If you have research papers you are trying to promote, we will review them to see if they are a good fit for our global audience. At a minimum, papers need to be well researched and documented, relevant to the semiconductor ecosystem, and free of marketing bias. There is no cost involved for us po... » read more

Automatic Layout Generator Targeting Region-based Layouts for Advanced FinFET-Based Full-Custom Circuits (UT Austin/NVIDIA)
By Technical Paper Link - 15 Dec, 2022 - Comments: 0

A technical paper titled "AutoCRAFT: Layout Automation for Custom Circuits in Advanced FinFET Technologies" was published by researchers at UT Austin and NVIDIA. "This paper presents AutoCRAFT, an automatic layout generator targeting region-based layouts for advanced FinFET-based full-custom circuits. AutoCRAFT uses specialized place-and-route (P&R) algorithms to handle various design cons... » read more

Lithography Modeling: Data Augmentation Framework
By Technical Paper Link - 17 Nov, 2022 - Comments: 0

A new technical paper titled "An Adversarial Active Sampling-based Data Augmentation Framework for Manufacturable Chip Design" was published by researchers at the University of Texas at Austin, Nvidia, and the California Institute of Technology. Abstract: "Lithography modeling is a crucial problem in chip design to ensure a chip design mask is manufacturable. It requires rigorous simulation... » read more

Technical Paper Round-Up: Aug 23
By Linda Christensen - 23 Aug, 2022 - Comments: 0

New technical papers added to Semiconductor Engineering’s library this week. [table id=46 /] Semiconductor Engineering is in the process of building this library of research papers. Please send suggestions (via comments section below) for what else you’d like us to incorporate. If you have research papers you are trying to promote, we will review them to see if they are a good fit for... » read more

Beyond 5nm: Review of Buried Power Rails & Back-Side Power
By Technical Paper Link - 19 Aug, 2022 - Comments: 0

A new technical paper titled "A Holistic Evaluation of Buried Power Rails and Back-Side Power for Sub-5 nm Technology Nodes" is presented by researchers at UT Austin, Arm Research, and imec. Find the technical paper here. Published July 2022. S. S. T. Nibhanupudi et al., "A Holistic Evaluation of Buried Power Rails and Back-Side Power for Sub-5 nm Technology Nodes," in IEEE Transactions... » read more

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