tag: verification

Exercising State Machines with Command Sequences
By Siemens EDA - 24 Mar, 2021 - Comments: 0

Almost every non-trivial design contains at least one state machine, and exercising that state machine through its legal states, state transitions, and the different reasons for state transitions is key to verifying the design’s functionality. In some cases, we can exercise a state machine simply as a side-effect of performing normal operations on the design. In other cases, the state machine... » read more

An Insider’s View Of Verifying Custom RISC-V Processor Cores
By Shubhodeep Roy Choudhury - 15 Mar, 2021 - Comments: 0

By Shubhodeep Roy Choudhury, Valtrix Systems, and Lee Moore, Imperas Software Supporting images courtesy of Bill McSpadden, Seagate Technology This article is derived from a talk at the RISC-V Summit in December 2020 that Bill McSpadden, principal verification engineer at Seagate Technology, gave on the challenges and experiences his team faced in the verification of two custom RISC-V proce... » read more

Nine Effective Features Of NVMe Verification IP For PCIe-Based SSD Storage
By Siemens EDA - 10 Mar, 2021 - Comments: 0

Non-Volatile Memory Express (NVMe) is a new software interface optimized for PCIe Solid State Drives (SSD). This paper provides an overview of the NVMe specification and examines some of its key features. We will discuss its pros and cons, compare it to other conventional technologies, and point out key areas to focus on during its verification. You will learn how NVMe Questa Verification IP... » read more

Using 5nm Chips And Advanced Packages In Cars
By Ed Sperling - 10 Mar, 2021 - Comments: 1

Semiconductor Engineering sat down to discuss the impact of advanced node chips and advanced packaging on automotive reliability with Jay Rathert, senior director of strategic collaborations at KLA; Dennis Ciplickas, vice president of advanced solutions at PDF Solutions; Uzi Baruch, vice president and general manager of the automotive business unit at OptimalPlus; Gal Carmel, general manager of... » read more

Design Issues For Chips Over Longer Lifetimes
By Ed Sperling - 08 Mar, 2021 - Comments: 0

Semiconductor Engineering sat down to discuss the myriad challenges associated with chips used in complex systems over longer periods of time them with Jean-Marie Brunet, senior director for the Emulation Division at Siemens EDA; Frank Schirrmeister, senior group director for solution marketing at Cadence; Maurizio Griva, R&D Manager at Reply; and Laurent Maillet-Contoz, system and architec... » read more

The Single Greatest Opportunity For Open Source
By Brian Bailey - 25 Feb, 2021 - Comments: 7

Next week, I will be moderating a panel at the virtual DVCon on the subject of open-source verification. I thought it would be good to advertise the event on LinkedIn to see if anyone wanted to send me well-structured questions for the panelists. What happened surprised me a little because the discussions almost exclusively went to the need for open-source verification tools. In my opinion, the... » read more

Advancing IC And Systems Design With The Digital Twin
By Joseph Sawicki - 25 Feb, 2021 - Comments: 0

As many of you may have seen, we’ve passed a major milestone since Siemens announced its intent to acquire Mentor Graphics four years ago. As of January 1, 2021, “Mentor, a Siemens business” has become “Siemens EDA” and remains a segment of the larger Siemens Digital Industries Software organization. Siemens is bringing together one of the world’s most comprehensive EDA portfolios w... » read more

Verification Knowledge At Your Fingertips
By Rob van Blommestein - 25 Feb, 2021 - Comments: 0

If you’re like most engineers, you’re curious about how other engineers tackle some of the most difficult challenges. What can you absorb from them and apply to your own projects? Learning from experience has tremendous value but learning from others’ experiences is arguably more valuable since the cost to acquire that knowledge is significantly cheaper. At OneSpin, we’ve lowered... » read more

When Is Verification Done?
By Ann Mutschler - 25 Feb, 2021 - Comments: 0

Even with the billions of dollars spent on R&D for EDA tools, and tens of billions more on verification labor, only 30% to 50% of ASIC designs are first time right, according to Wilson Research Group and Siemens EDA. Even then, these designs still have bugs. They’re just not catastrophic enough to cause a re-spin. This means more efficient verification is needed. Until then, verificati... » read more

Big Challenges In Verifying Cyber-Physical Systems
By Ed Sperling - 25 Feb, 2021 - Comments: 0

Semiconductor Engineering sat down to discuss cyber-physical systems and how to verify them with Jean-Marie Brunet, senior director for the Emulation Division at Siemens EDA; Frank Schirrmeister, senior group director for solution marketing at Cadence; Maurizio Griva, R&D Manager at Reply; and Laurent Maillet-Contoz, system and architect specialist at STMicroelectronics. This discussion was... » read more

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