Power Semi Wars Begin

By Mark LaPedus - 23 Oct, 2019 - Comments: 1

Several vendors are rolling out the next wave of power semiconductors based on gallium nitride (GaN) and silicon carbide (SiC), setting the stage for a showdown against traditional silicon-based devices in the market. Power semiconductors are specialized transistors that incorporate different and competitive technologies like GaN, SiC and silicon. Power semis operate as a switch in high-volt... » read more

Curvilinear Full-Chip ILT

By Ed Sperling - 17 Oct, 2019 - Comments: 0

Leo Pang, chief product officer and executive vice president at D2S, talks about the speed improvements with full-chip inverse lithography technology, why it is so critical in stitching together large chips, and how this approach differs from traditional litho approaches. » read more

Reducing Costly Flaws In Heterogeneous Designs

By Ed Sperling - 08 Oct, 2019 - Comments: 0

The cost of defects is rising as chipmakers begin adding multiple chips into a package, or multiple processor cores and memories on the same die. Put simply, one bad wire can spoil an entire system. Two main issues need to be solved to reduce the number of defects. The first is identifying the actual defect, which becomes more difficult as chips grow larger and more complex, and whenever chi... » read more

The Unexpected Impact Of Lots On Hold

By Marie Ryan - 08 Oct, 2019 - Comments: 0

One of the biggest bottlenecks in any Subcon is Lots on Hold. The problem occurs many times a week on most factory floors. It’s something you’ve grown to loathe or endure. But, is there something you can do to reduce the amount of time lots spend on hold? In this article, we will explain what Lots on Hold are and how you can make the process less painful for your team and help improve on-ti... » read more

The Hidden Potential Of Test Engineers

By Marie Ryan - 10 Sep, 2019 - Comments: 0

Design engineers are seen as the cornerstone of new projects in many semiconductor companies, working away with the team to design the next product and making sure it meets all specifications. We pay little thought to the test engineer, who works in the shadows designing algorithms, hardware and software that could pass or fail each die. The test engineer is the last line of defense between... » read more

New Technologies To Support 3D-ICs

By Brian Bailey - 04 Sep, 2019 - Comments: 0

Semiconductor Engineering sat down to discuss changes required throughout the ecosystem to support three-dimensional (3D) chip design with Norman Chang, chief technologist for the Semiconductor Business Unit of ANSYS; John Park, product management director for IC packaging and cross-platform solutions at Cadence; John Ferguson, director of marketing for DRC applications at Mentor, a Siemens Bus... » read more

Wanted: More Fab Tool Part Standards

By Mark LaPedus - 15 Aug, 2019 - Comments: 0

As chipmakers ramp up the next wave of processes and grapple with how to reduce defect levels, they are encountering problems from an unlikely source—components inside of the fab equipment. Defects are unwanted deviations in chips, which impact yields and device performance. Typically, they are caused by an unforeseen glitch during the process flow. But a lesser-known problem involves defe... » read more

Process Window Optimization

By Ed Sperling - 07 Aug, 2019 - Comments: 0

David Fried, vice president of computational products at Lam Research, examines increasing process variation and interactions between various types of variation, why different approaches are necessary to improve yield and continue scaling. » read more

Yield Impact For Wafer Shape Misregistration-Based Binning For Overlay APC Diagnostic Enhancement

By KLA - 05 Aug, 2019 - Comments: 0

By David Jayez, Kevin Jock, Yue Zhou and Venugopal Govindarajulu of GlobalFoundries, and Zhen Zhang, Fatima Anis, Felipe Tijiwa-Birk and Shivam Agarwal of KLA. 1. ABSTRACT The importance of traditionally acceptable sources of variation has started to become more critical as semiconductor technologies continue to push into smaller technology nodes. New metrology techniques are needed to pur... » read more

Big Shifts In Big Data

By Ed Sperling - 09 Jul, 2019 - Comments: 0

The big data market is in a state of upheaval as companies begin shifting their data strategies from "nothing" or "everything" in the cloud to a strategic mix, squeezing out middle-market players and changing what gets shared, how that data is used, and how best to secure it. This has broad implications for the whole semiconductor supply chain, because in many cases it paves the way for ... » read more

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Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

Why Small Fab And Assembly Houses Are Thriving

Megafabs churning out the most advanced processors are not the only game in town.

by Bryon Moyer

tag: yield