The Future Of FinFETs

The number of questions about finFETs is increasing—particularly, how long can they continue to be used before some version of gate-all-around FET is required to replace them.

This discussion is confusing in many respects. For one thing, a 7nm finFET for TSMC or Samsung is not the same as a 7nm finFET for Intel or GlobalFoundries. There are a bunch of other nodes being proposed, as well, including 8nm, 6nm and 4nm, but so far there are no reference points to indicate what those numbers really mean.

What is clear, though, is that at some point finFETs will need to be replaced. Fins get taller and thinner at each new node, regardless of which numbers are used, and at some point they start running into fundamental physics. The taller a building, the more complex the support structure needs to be. It’s the same for fins on a FET. This is why research houses such as Imec and Leti have been so focused on horizontal and vertical nanowires/nanosheets. At some point changes will be necessary.

To some extent, this is a replay of conversations that began at 45nm, when chipmakers first began looking seriously at finFETs. That was the point where leakage current became more of a design issue than dynamic power, and finFETs were the best way to actually turn off these tiny switches. Without finFETs, the difference between on and off was somewhat analogous to turning off a leaky faucet. There was definitely a difference between on and off, but off became an increasingly relative term. Over time, batteries would drain even if these devices were not being used.

With GAA FETs, the problem is more about manufacturability than leakage, although leakage has been growing ever since the first finFETs were introduced. GAA approaches are expected to help with that for at least a couple nodes, which these days could mean a decade or more.

The downside of moving to GAA FETs is the loss of continuity in the fab. In manufacturing, change of this magnitude is significant and expensive. One of the reasons Intel introduced finFETs at 22nm rather than 14nm is that it only wanted to grapple with one problem at a time. It postponed double patterning until 14nm as a way of getting finFETs out the door more quickly. The next process nodes will bring new lithography, new materials, and potentially new demands for reliability from automotive AI systems. The fewer changes required, the fewer issues that potentially can affect yield and time to market.

It’s also not entirely clear when there will be enough customers and enough volume to drive demand at the next nodes. Mobile devices will continue to drive demand, but perhaps only at one or two foundries. High-performance computing, which now includes cloud, AI, cryptocurrency mining and augmented/virtual reality, as well as networking infrastructure, are starting to shift to different chip architectures and packaging approaches. While they may follow the feature shrinking roadmaps, they also may opt for much more heterogeneous approaches that rely more on parallelism than putting everything on one chip. In short, they will migrate to whichever path offers them better performance for the lowest price with a solid roadmap for future revs.

All of this creates a lot of uncertainty for foundries, and that uncertainty has been building for some time. That means there will be a lot of increasingly frenzied discussions about next-gen transistor structures, but actual production may be more about waiting until a competitor actually commits to making new devices. So far, there is nothing but talk.

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