The Week In Review: Design

Tools
Synopsys debuted new versions of its circuit simulation and custom design products. FineSim SPICE provides 2X faster simulation and Monte Carlo analysis speed, CustomSim FastSPICE offers 2X speed-up for post-layout SRAM simulation and maintains multi-core scalability by providing additional 2X speed-up on four cores, and HSPICE delivers 1.5X speed-up for large post-layout designs, according to the company. Meanwhile, Custom Compiler adds device-level pattern routing that can extract patterns from a hand-created layout and reapply those patterns to other connections.

Mentor announced the latest version of its FloMASTER 1D thermo-fluid system modeling product. It provides automated connectivity to 3D CAD design tools and can automatically abstract the 3D descriptions of piping networks into a collection of connected FloMASTER components.

Plunify launched its Plunify Cloud client, an interface to the Xilinx Vivado design suite for development, optimization, testing and deployment of FPGA designs, on the Tencent Cloud FPGA Ecosystem.

Concept Engineering uncorked an online, reactive schematic visualization solution for use in automotive service centers that renders schematics of specific problem areas in automotive electrical systems based on Diagnostic Trouble Codes (DTC) generated by the vehicle or technician input.

Photonics
Synopsys updated its photonics design tools with the first release of OptoDesigner since the company’s acquisition of PhoeniX Software. The tool for layout and verification of photonic ICs adds a new high-level filter synthesis module and enhanced layout automation for phase-insensitive photonic waveguide routing. RSoft also saw updates to its S-Matrix/PDK Generation Utility and added support for parametric custom PDK components, among other additions.

VPIphotonics integrated its photonics simulation environment with Mentor’s Tanner EDA IC layout environment for a complete photonic circuit modeling environment that allows designers to benchmark circuit performance in simulated system applications.

TowerJazz released an initial silicon photonics design kit for its PH18 Silicon Photonics process based on Mentor’s Calibre nmPlatform. It includes design kits for the Calibre nmDRC and nmLVS tools. There are plans to add optical components in future releases.

Deals
VeriSilicon inked an agreement with Arteris IP for multiple licenses of Arteris FlexNoC interconnect IP, which it will use as the on-chip communications backbone of SoCs for the data center, automotive and other applications. VeriSilicon cited shorter chip development time and lowered physical implementation difficulty.

Standards
Si2’s Compact Model Coalition (CMC) approved two IC design simulation standards for gallium nitride (GaN) semiconductors: the Advance SPICE Model for GaN and the MIT Virtual Source GaN-HEMT model. GaN devices target high-power and high-frequency applications, including satellite communications, radar, cellular, broadband wireless systems, and automotive.

Numbers
Market research firm IC Insights raised its 2018 IC market forecast from 8% to 15%, based on the continued strength of memory markets. The DRAM forecast was raised to 37% (from 13%), while the NAND flash forecast was raised to 17% (from 10%). IC Insights expects DRAM ASP to register a 36% jump in 2018 as compared to 2017, when the DRAM ASP surged 81%. The NAND flash ASP is forecast to increase 10% this year, after jumping by 45% in 2017. The DRAM market is forecast to be by far the largest single product category in the IC industry.

Events
DATE 2018: Mar. 19-23 in Dresden, Germany. The conference focuses on hardware and software design, test and manufacturing of electronic circuits and systems. Features include in-depth tutorials, business panels, and keynotes on safety for autonomous vehicles and mapping circuits to DNA.

Decoding Formal: Mar. 20 in San Jose, CA. This quarterly event hosted by Oski Technology focused on formal verification techniques will feature a keynote address by cryptography expert Mike Hamburg, who will discuss how formal analysis contributed to his discovery of the Meltdown and Spectre security flaws, as well as talks by Cisco on applying formal to networking chips and Arteris IP on formal methods and ISO 26262.

2018 CEO Outlook: Apr. 5, 5:30 p.m. – 8:30 p.m. in San Jose, CA. This panel, hosted by the ESD Alliance, will bring together CEOs Dean Drako of IC Manage, Grant Pierce of Sonics, Wally Rhines of Mentor, and Simon Segars of Arm for their views of the major trends and opportunities in the semiconductor design ecosystem, including an interactive, moderated audience discussion.

D&R IP-SoC Day: Apr. 5 in Santa Clara, CA. The one-day event will discuss trends in IP including AI and deep learning architectures, RISC-V, eFPGAs, and IP management and reuse.