The Week In Review: Design

Embedded vision DSP; Cadence updates IC design platform; eFPGA IP on TSMC 16FFC.


Tools & IP
Cadence unveiled its latest DSP for embedded vision and AI, Tensilica Vision Q6 DSP. The DSP is built on a 13-stage processor pipeline and new system architecture designed for use with large local memories, and achieves 1.5GHz peak frequency and 1GHz typical frequency at 16nm. Compared to its predecessor, it offers 1.5X greater vision and AI performance than its predecessor and 1.25X better power efficiency. It is backwards compatible with Vision P6 DSP software.

Cadence also debuted enhancements to its Virtuoso custom IC design platform, which enables simultaneous edits across multiple process design kits and technologies and allows package, photonics, IC analog and RF design through a single platform. Key improvements focus on design and layout for advanced nodes which the company says improves layout productivity by up to 50%, as well as changes to analog design analysis that improves Virtuoso ADE simulation throughput by up to 3X.

Fraunhofer IIS uncorked its first JPEG XS codec implementation for video production. JPEG XS allows transferring high-resolution video data over standard Ethernet or other wired connections and is optimized for the use with mezzanine compression when high image quality data has to be transferred via limited bandwidth or has to be processed with limited computing resources.

Aldec and Northwest Logic demonstrated a PCIe solution with over 6 GB/s throughput using Aldec’s HES-XCVU9P-QDR UltraScale+ board with Northwest Logic’s Expresso 3.0 core for PCI Express and AXI DMA Back-End Core.

Flex Logix’s EFLX4K eFPGA IP core, in both Logic and DSP versions, has been fully validated on TSMC’s 16FFC process. The GDS is also compatible with TSMC 16FF+. Evaluation boards are available that integrate the EFLX200K validation chip.

CAST ported its high performance lossless compression IP to Achronix’s line of FPGA and eFPGA products. The collaboration aims to create a low-power solution to facilitate moving and storing big data.

Fraunhofer IIS’s MPEG-H TV Audio System was integrated into products from Ericsson and Innopia. Ericsson’s contribution-path encode/decode solution allows broadcasters to generate an MPEG-H bitstream with all the necessary metadata at the site of an event and transport it back to the studio for further processing and final emission. Innopia’s set-top-box for the Korean market incorporates an ATSC 3.0 tuner that can connects to any TV with HDMI inputs to receive terrestrial UHD TV broadcasts, along with broadband-delivered content, with MPEG-H 3D Audio.

IP Security Assurance PWG: Apr. 17, 10 a.m. – noon in Santa Clara, CA. Initial meeting for an Accellera Proposed Working Group to assess whether there’s interest and feasibility in defining an automated systematic approach to integrating security assurance collateral. Participants need not be from Accellera member companies.

All You Need to Know About Inbound Digital Marketing: Apr. 26 in Milpitas, CA. The ESD Alliance will host a workshop focused on new marketing strategies and techniques for EDA, IP, and services companies. Nicolas Athanasopoulos, OneSpin’s Head of Digital Strategy and Dave Kelf, Chief Marketing Officer at Breker Verification Systems will lead the workshop.

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