The Week In Review: Design

M&A
ANSYS finalized its acquisition of OPTIS. Founded in 1989, OPTIS provided software for scientific simulation of light, human vision and physics-based visualization. The acquisition boosts the company’s automotive simulation portfolio with radar, lidar and camera simulation. Terms were not disclosed.

IP
Arm debuted the Cortex-M35P processor. Aimed at IoT applications, the IP combines anti-tampering technology and software isolation to protect against physical and close proximity side-channel attacks, including power and electromagnetic analysis. A safety package to support ISO 26262 certification is available. Additionally, Arm’s CryptoCell and CryptoIsland security IP are now available hardened with side-channel attack protection.

Cadence unveiled three new verification IPs: CoaXPress VIP offering for high-speed imaging, the HyperRAM high-speed memory VIP, and a VIP offering for the new JEDEC Universal Flash Storage (UFS) 3.0 specification. The CoaXPress interface standard provides high-speed serial communication over coaxial cable for automated acquisition and analysis of video and images, HyperRAM is a high-performance 333MB/sec read performance memory based on the HyperBus interface, and the UFS 3.0 specification doubles throughput bandwidth from 1333MB/s in UFS 2.1 to 2666MB/s.

MIPS uncorked a new high performance IP core in its midrange 32-bit product lineup, the I7200 multi-threaded multi-core processor. Targeted at high bandwidth modem subsystems in Advanced LTE Pro and upcoming 5G smartphone SoCs, as well as networking ICs, it supports simultaneous multi-threading with thread prioritization and zero cycle context switching, configurable memory management, and deterministic ScratchPad RAMs. According to the company, the I7200 delivers 50% higher performance in less than 20% area increase than the previous generation.

PLDA launched XpressCCIX PCIe controller IP to support the Cache Coherent Interconnect for Accelerators. XpressCCIX supports the CCIX ESM standard up to 25Gbps, as well as transparent upgrade to PCIe 5.0 (Gen5) without changes to the application logic, reduced gate count by implementing an optimized 512-bit datapath, and the ability to implement custom cache coherency mechanisms.

Cadence prototyped its first IP interface in silicon for a preliminary version of the DDR5 standard being developed in JEDEC. The test chip was fabricated in TSMC’s 7nm process and achieves a 4400 megatransfers per second data rate, 37.5% faster than the fastest commercial DDR4 memory at 3200MT/sec.

Standards
The DDR PHY Interface (DFI) Group released version 5.0 of the specification for interfaces between high-speed memory controllers and PHY interfaces. The new version adds protocol support for the newest DDR and low-power memory technologies, as well as a PHY-independent training mode. Other interface improvements include lower power enhancements, providing a PHY-independent boot sequence, expanding frequency change support, and defining new controller-to-PHY interface interactions.

The MIPI Alliance published MIPI I3C Host Controller Interface (HCI) v1.0, a specification that defines the building of a common software driver interface to support compliant MIPI I3C host controller (master device) hardware implementations from multiple vendors and allow for vendor-specific extensions and optimizations. MIPI I3C HCI v1.0 includes support for MIPI I3C main master device operation on the I3C bus, I3C data rates, and two modes of operation.

Deals
Softbank finalized a joint venture with Chinese investors. Under the terms of the deal, Softbank’s Arm business unit will have 49% stake in the business while China’s HOPU-ARM Innovation Fund will control 51%. HOPU-ARM is funded by China Investment Corp., Silk Road Fund, Temasek, Shenzhen Shum Yip Group and Arm, according to China Tech News. The deal is considered a big win for China because it allows easier access to advanced processor IP. An IPO is expected by 2022, according to Nikkei Asian Review. 

Canaan Creative licensed Arteris IP’s FlexNoC interconnect IP as the on-chip communications backbone of its next generation artificial intelligence ASIC, managing communications between multiple on-chip hardware accelerators. Canaan cited power consumption, bandwidth/latency, and reliability as reasons for the choice.

Sondrel plans to standardize its IC designs using NetSpeed Systems’ product line of interconnect fabric, including Orion fabric IP, Gemini cache coherent fabric IP, and Pegasus Last Level cache. Sondrel’s high end application processor and analytics platforms, implemented in 16nm processes and below, already use NetSpeed’s cache coherent interconnect and last level cache solution.

Andes Technology adopted UltraSoC’s embedded analytics technology and RISC-V processor trace solution for use in its AndesCore range of RISC-V processors, including the high-end 32-bit N25 and 64-bit NX25 targeted at high-speed control tasks.

Cambricon adopted Synopsys’ HAPS-80 prototyping platform for verification of a next-generation AI processor product. Cambricon cited performance and scalability for complex software tests and real-world interface testing, and also used the prototyping system on its Cloud Smart Chip.

Realtek used Cadence’s Innovus Implementation System for its 28nm Digital TV SoC production tapeout. Realtek noted an area improvement and reduced power, and cited higher capacity enabling larger top-level blocks, which reduced hierarchy and complexity of the SoC’s top level.

Aldec teamed up with Tamba Networks to launch an FPGA solution aimed at the High Frequency Trading market. The HES-XCVU9P-QDR UltraScale+ board uses Tamba Networks 10G Ethernet MAC IP Core for Ultra-Low Latency Ethernet and has 2x 100 Gb/s QSFP28 cages plus QDR-II+ or DDR4 memory modules to provide high throughput for algorithm acceleration and data processing using the PCIe interface protocol.

TSMC Certifications
ANSYS’ RedHawk and Totem tools for power noise and reliability signoff were certified for TSMC’s 5nm FinFET process and validated for TSMC’s Wafer-on-Wafer (WoW) and Chip-on-Wafer-on-Substrate (CoWoS) advanced packaging technologies.

Cadence’s digital, signoff and custom/analog tools were certified for TSMC’s 5nm and 7nm+ processes. Features available for the 7nm process are also available for the 5nm and 7nm+ process, including cut-metal handling throughout the design flow, via-pillar support, clock mesh and bus-routing, along with new enhancements focused on EUV support at key layers. The full suite also supports the new TSMC WoW stacking technology.

Several tools in Mentor’s Calibre nmPlatform and Analog FastSPICE Platform have been certified by TSMC for the latest versions of TSMC’s 5nm FinFET and 7nm FinFET Plus processes. Additionally, Calibre nmPlatform tools have been updated in support of TSMC’s WoW stacking technology.

Synopsys’ Design Platform, including IC Compiler II, was certified for TSMC’s 5nm FinFET and 7nm FinFET Plus. Updates include enhanced circuit simulation modeling for 5-nm FinFET devices and platform-wide support for multi-die integration using TSMC’s WoW technology.

Additionally, Synopsys is developing foundation IP for TSMC’s 22nm ultra-low power (ULP) and ultra-low leakage (ULL) processes, including logic libraries, embedded memories, and one-time programmable non-volatile memories.

Arm’s Artisan physical IP will be used in TSMC’s 22nm ultra-low power (ULP) and ultra-low leakage (ULL) platforms for Arm-based SoCs targeted at mainstream mobile and IoT devices. The physical IP includes memory compilers optimized for the low-leakage and low-power requirements, standard cell libraries including power-management kits, and thick-gate oxide cells to help optimize low-leakage power.

Numbers
ANSYS reported first quarter financial results with revenue of $282.9 million. On a GAAP basis, earnings per share for Q1 2018 were $0.98, while non-GAAP EPS stood at $1.20. The company changed to a new reporting standard; under the previous rules, revenue for the first quarter was $284.6, up 12.3% from the first quarter last year. Earnings per share, on a GAAP basis, were $1.00, up 37% from $0.73 in Q1 2017, while non-GAAP earnings were $1.22 per share, also up 37% from $0.89 in the same quarter last year.