The Week In Review: Design

Test tools updated; neural inferencing; RISC-V cores.


GlobalFoundries formed Avera Semiconductor, a wholly-owned subsidiary focused on custom ASIC designs. While Avera will use its relationship with GF for 14/12nm and more mature technologies, it has a foundry partnership lined up for 7nm. The new company’s IP portfolio includes high-speed SerDes, high-performance embedded TCAMs, ARM cores and performance and density-optimized embedded SRAMs.

Real Intent debuted a new tool to assess “X” sources and design initialization at RTL. Components of Meridian RXV include analysis of the design initialization requirements and status, optimization of the reset scheme, reporting on the susceptibility of a design to the masking of functional bugs due to X-optimism, and debug reporting.

Synopsys introduced new test point functionality to its test products. The implementation of the test points is designed to avoid introducing routing congestion and minimize area impact by enabling multiple test points to share a single test register based on physical proximity. Using both DFT and synthesis tools, the company says it can reduce silicon test costs by an average of 40%. Synopsys also added new soft-error analysis functionality to its SpyGlass DFT ADV tool to aid in improving ISO 26262 functional safety metrics. The tool calculates Single Point Fault Metrics using static analysis and identifies the minimum number of regular flops that need to be replaced with error-tolerant ones to meet requirements. Analysis can be performed early in the design flow on either RTL- or gate-level netlists.

Mentor released automotive-grade automatic test pattern generation (ATPG) technology for its Tessent TestKompress software including a suite of fault models and test pattern generation applications that target defects at the transistor level inside cells, between adjacent cells, and in the interconnect based on critical area. The company says the technology allows for better DPPM levels at lower cost than traditional methods.

Synopsys’ DesignWare STAR Memory System added new memory BIST, repair, and diagnostic capabilities for embedded MRAM-based designs. It initially supports GlobalFoundries’ eMRAM on the 22FDX process.

Flex Logix revealed a new product line focused inferencing for neural networks. NMAX has a modular, scalable architecture and uses a fraction of the DRAM bandwidth of existing neural inferencing solutions, according to the company. NMAX tiles consist of 512 MACs with local SRAM and has ~1 TOPS peak performance in 16nm. The tiles can be arrayed in configurations up to >100 TOPS peak performance.  NMAX will be available in the second half of 2019.

Cadence uncorked a DSP core focused on high-performance far-field processing and AI-based speech recognition processing. Tensilica HiFi 5 DSP has a five very long instruction word (VLIW)-slot architecture capable of issuing two 128-bit loads per cycle. For audio processing, it supports eight 32×32-bit or 16 16×16-bit MACs per cycle with eight optional single-precision floating-point MACs per cycle. For neural network processing, it supports 32 16×8 or 16×4 MACs per cycle with optional 16 half-precision floating-point MACs per cycle. It offers 2X MACs for audio processing and 4X MACs for neural network processing over its predecessor.

SiFive released a new line of high performance RISC-V cores. The SiFive Core IP 7 Series provides a heterogenous, customizable architecture that allows the different cores in the series to be combined in a single coherent core complex. The E7 Series comprises 32-bit cores with hard real-time capabilities, S7 has a high performance 64-bit architecture for embedded markets, and U7 is a Linux-capable 64-bit applications processor with a configurable memory architecture for domain-specific customization.

Arteris IP unveiled the fourth version of its FlexNoC interconnect IP along with a companion AI Package. New capabilities include: automated AI topology generation for mesh, ring and torus networks; intelligent multicast; source synchronous communications; and HBM2 and multichannel memory support.

VeriSilicon announced Bluetooth Low Energy (BLE) 5.0 RF IP based on GlobalFoundries’ 22FDX FD-SOI process. The IP includes a BLE 5.0 compliant transceiver and supports GFSK modulation and demodulation. Sensitivity can be tested up to -9dBm with less than 7mW power dissipation in typical conditions.

Imagination debuted Global Navigation Satellite System (GNSS) IP supporting GPS, GLONASS, Galileo, and BeiDou as well as several Satellite-Based Augmentation Systems (SBAS) including WAAS and EGNOS. The IP is optimized for for ultra-low power consumption for battery powered remote IoT sensors, edge devices, and wearables. Imagination also announced a new generation of its image compression technology. PVRIC4 features a dual-pipeline framebuffer compression engine for random-access visually lossless compression. A new lossy pipeline can compress ‘noisy’ images if the lossless pipeline can’t reach 50% compression. It is targeted to reduce costs for DTV, smartphone, and tablet SoCs.

Rambus reported third quarter financial results with revenue of $59.8 million. On a GAAP basis, Q3 2018 had a net loss of $0.97 per share while non-GAAP loss per share was $0.01. The company changed to new accounting standards this year; under the previous method, revenue was $99.8 million for the quarter, up 0.7% from $99.1 in the same quarter last year. Loss per share was $0.65 on a GAAP basis compared to income of $0.07 per share in Q3 2017. Non-GAAP income was $0.22 per share, up from $0.19.

Luc Seraphin has been appointed president and CEO of Rambus. Before becoming the company’s interim CEO in June 2018, Seraphin was Senior Vice President & General Manager of Rambus’ Memory and Interfaces Division. He previously spent 18 years at Avago with positions in sales, marketing and general management.

There’s a new show in town. Next year, the ESD Alliance will present ES Design West with a focus on IP, EDA, embedded software, design services, and infrastructure. Along with a dedicated conference track, there will be presentations and panels on the show floor. Co-located with SEMICON West, it will be held July 9-11 in San Francisco, CA.

ICCAD: Nov. 5-8 in San Diego, CA. The technical conference focused on emerging technology challenges in EDA features keynotes on IoT and Cloud systems, DARPA’s Electronics Resurgence Initiative, and the impact of technology trends on EDA tools and flows. Special sessions, tutorials, and workshops are also part of the program.

IEEE Rebooting Computing Week: Nov. 5-9 in Tysons, VA. The first two days will focus on the International Roadmap for Devices and Systems, while the International Conference on Rebooting Computing will be held the 7-9th. The conference focuses on novel computing approaches, including algorithms and languages, system software, system and network architectures, new devices and circuits, and applications of new materials and physics.

Phil Kaufman Award Ceremony and Dinner: Nov. 7, 6:30 – 9:30 p.m. in San Jose, CA. This year’s award honors Thomas W. Williams for his contributions to test automation including Level Sensitive Scan Design and subsequent enhancements to IC testing including adaptive scan.

RISC-V Summit: Dec. 3-6 in Santa Clara, CA. The first annual conference and exhibition dedicated to the RSIC-V ISA ecosystem. Training sessions, workshops, and presentations will be available, followed by a day for Foundation members.

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