What chip industry engineers watched in 2024.
In 2024, hot topics included challenges involving chiplets and heterogeneous integration, AI, data management, MCUs, power semis, software-defined vehicles, sensors, adaptive test, yield tracking, safety monitoring, security, and much more.
Top 5 most watched videos in 2024:
See below for all videos published in 2024 across our channels:
Manufacturing, Packaging And Materials
Test, Measurement And Analytics
Power, Performance
Automotive, Security And Pervasive Computing
Systems And Design
Emerging Technologies Driving Heterogeneous Integration looks at new architectures, opportunities, and challenges as chipmakers move from monolithic architectures to chiplets.
Secure Movement Of Data In Test explores the impact of heterogeneous integration on how data is used in manufacturing.
Speeding Up Acoustic Wafer Inspection delves into why rotational scanning shrinks inspection time in complex chips and packages.
Real-Time Safety Monitoring explains how to measure a chip’s health during operation and throughout its lifecycle, and how and when to take prescriptive action.
Making Adaptive Test Work Better covers ways to optimize testing around different data sources, how to partition data between the edge and the cloud, and ensure security.
Overlay Optimization In Advanced IC Substrates talks about the intricacies of overlay, the pros and cons of glass substrates, and what’s needed for high-volume manufacturing.
Cost And Quality Of Chiplets digs into adaptive test and why it is becoming necessary in heterogeneous designs.
Yield Tracking In RDL shows how to identify defects in panel-level packages, and why that’s needed for generative AI in data centers.
Reducing Power In Data Centers outlines new approaches to improving utilization while reducing guard-banding.
Using Deep Data For Improved Reliability Testing extols the benefits of using internal data to determine failure rates and how close an individual device is to failure.
Next-Gen High-Speed Communication In Data Centers discusses the rapid increase in different types of optics and optical scenarios under development.
Real-World Applications Of Computational Fluid Dynamics imagines a future filled with “what if” scenarios, and how faster processing is revolutionizing different industries.
Making Electronics More Efficient evaluates the impact of disaggregation and chiplets, pitfalls with partitioning and modeling, and what’s missing out of the design flow.
Challenges With Chiplets And Power Delivery weighs up the benefits of heterogeneous integration against concerns such as thermal dissipation, uneven aging, and stress.
New Issues In Power Semiconductors looks at issues in integrating these devices with others, different packaging impacts, and degradation over time.
Why Connectivity Is Changing Microcontrollers examines the proliferation of “connected controllers,” capable of running a full network stack, and where one size no longer fits all.
Toward Software-Defined Vehicles contends the abstraction level for ECUs needs to be raised, looks at time and cost to design and test, plus what’s needed on the software side.
MCU Changes At The Edge delves into functions and features such as machine learning, off-chip and on-chip memory, low power, high performance, and embedded security.
Adapting To Evolving IC Requirements focuses on eFPGAs’ ability to adapt to new security threats and changing workloads, and how they can re-route data if a problem arises.
Sensor Fusion Challenges In Automotive discusses the growing importance of 4D sensing, future-proofing designs, and why a single, centralized architecture is so critical.
Rethinking Chip Economics lays out reasons why the complexity and costs of developing chips increases as more features and functions are added.
Changes And Challenges In Auto MCUs explains why automakers are shifting their emphasis from custom hardware to differentiating in software.
How To Stop Row Hammer Attacks deep dives into this security issue, why it passes virtually unnoticed by error correction technology, and how to stop it.
What’s Changing In DRAM looks at the way different memories are being mixed in the same design to deal with an explosion in data, but why that’s not a simple solution.
Distributed Voltage And Frequency Scaling Gaining Traction explains the benefits of DVFS, how it can improve battery life and performance, and how to embed it into a design.
The Evolution of HBM reviews the memory solution’s journey from 2.5D to AI everywhere with details on how the new HBM4 standard and custom HBM will impact PPA.
Using Formal For RISC-V Security digs into reasons why microarchitectures and custom coding on low-cost chips are a growing source of concern.
Scaling Performance In AI Systems shows how to minimize bottlenecks in data-intensive workloads across a variety of vertical markets, and why NoCs are increasingly essential.
Globally Asynchronous, Locally Synchronous Clocks evaluates locally asynchronous clocking schemes as a way to help engineers partition and prioritize data movement.
Working With Chiplets talks about the challenges of developing and integrating chiplets, how this differs from a homogeneous SoC, and what comes after HBM.
Data Routing In Heterogeneous Chip Designs delves into problems engineers are likely to encounter with multi-vendor chiplets, including communication issues.
Changes In Formal Verification explains why formal is essential for finding deadlocks, security holes, and Xprop issues in safety-critical and AI designs, with a view to chiplets.
Promises And Pitfalls Of SoC Restructuring looks at IP-XACT and how to sidestep data incompatibility issues in heterogeneous chip designs.
Electromigration And IR Drop At Advanced Nodes goes over the steps to achieve a DRC-clean, manufacturing-ready design at advanced nodes.
Challenges In RISC-V Verification details how to debug a multi-core chip and ensure it will be cache coherent and secure.
Cache Coherency In Heterogeneous Systems explores ways to minimize performance loss while maintaining flexibility to allow different processing elements to be prioritized.
Integration Challenges For RISC-V Designs defines which blocks need to talk to others, how to build in cache coherency, and the different interfaces in a complex system.
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