Week In Review: Design, Low Power

Tools
Imperas and Valtrix inked a multi-year distribution and support agreement that makes Imperas simulation technology and RISC-V reference models available pre-integrated within Valtrix STING for RISC-V processor verification. The combined solution covers the full RISC-V specification for user, privilege, and debug modes, including all ratified standard extensions, and the near ratified (stable) specifications for Bit Manipulation, Crypto (Scala), DSP, Hypervisor, and Vectors. STING plus Imperas is also upgradable to add support for custom instructions and extensions.

Synopsys’ Fusion Design Platform was used by Samsung Foundry to achieve first-pass silicon success for an advanced, high-performance and multi-subsystem SoC to validate the power, performance and area benefits of its next-generation, 3nm gate-all-around (GAA) process technology.

SiFive qualified Imperas models for the full range of the SiFive processor Core IP Portfolio. The simulation models support virtual prototypes for early software development before silicon devices are available and work with most industry-standard software IDEs and debuggers.

X-FAB released a reference design kit for Siemens EDA’s Tanner analog/mixed-signal (AMS) software. It can show the set-up of the PDK for the company’s XH018 180nm modular mixed-signal high-voltage CMOS process on Tanner AMS tools, with full coverage of the flow to design and simulate analog and mixed-signal ICs.

The ITER Organization will be working with Ansys to optimize electromagnetic structure design and performance for the ITER nuclear fusion plant, including improving project risk management, streamlining system development, and meeting critical safety requirements. Ansys’ Fluent will be used in validating the extreme cooling system, while Mechanical will be used in designing structural supports.

IP
Automotive semiconductor vendor AutoChips licensed Arteris IP’s FlexNoC interconnect IP for use in its next generation automotive SoCs. The company has previously licensed the product, starting in 2018. AutoChips cited the ability to meet functional safety, performance and time to market needs as well as engineering support.

Faraday Technology’s LPDDR4 and LPDDR4X combo PHY IP up to 4.2Gbps is now available in Samsung’s 14nm LPC process. The IP has two hardened configurations supporting both in-line rectangular and corner-edge placement. The built-in PLL enables improved input clock jitter performance. The solution also supports both KGD or packaged, single or multi DRAM chips.

Chips & design
Product engineering and lifecycle services company QuEST Global acquired Synapse Design, a provider of design services for ASICs and SoCs as well as analog/mixed-signal designs and software. “The acquisition of Synapse Design will enable us to provide comprehensive design services, consulting, and software development services to our semiconductor customers,” said Ajit Prabhu, Chairman & CEO of QuEST Global. Satish Bagalkotkar, President and CEO of Synapse Design, added, “This acquisition will combine our capabilities in providing design and consulting services with QuEST’s capabilities in providing embedded & software services and expertise in the convergence of electronics, software, and digital engineering innovations.” Based in San Jose, Calif., Synapse Design was founded in 2003. Terms of the deal were not disclosed.

Market research firm IC Insights expects IC sales to increase 24% this year to top $500 billion. It forecasts that 32 of the 33 major IC market categories defined by WSTS will see an increase in sales this year, with 29 of the product categories expected to see significant double-digit gains. Looking further forward, it predicts IC revenues exceeding $600 billion in 2023.

Wearables maker Deed included a number of Infineon products in its bracelet that uses gestures and biometric data to pick up calls and make payments. Deed used Infineon’s SECORA Connect for payments, XENSIV MEMS for voice recording, AIROC for Wi-Fi and Bluetooth, and PSoC 6 microcontroller.

HPC & quantum computing
In the latest TOP500 supercomputer rankings, the Japanese supercomputer Fugaku held onto the top spot on the list. Developed by Riken and Fujitsu and based on a custom Arm A64FX processor, it reached an HPL benchmark score of 442 Pflop/s, exceeding the performance of the second computer on the list, Summit, by 3X. It also led on the new HPL-AI benchmark, reaching 2 exaflops.

One new supercomputer entered the top ten: the Perlmutter system at NERSC at the DOE Lawrence Berkeley National Laboratory. The machine is based on the HPE Cray “Shasta” platform and a heterogeneous system with both GPU-accelerated and CPU-only nodes. Unveiled earlier this year, Perlmutter achieved 64.6 Pflop/s, putting the supercomputer at number 5 in the TOP500. It also reached number 6 on the Green500 with a power efficiency of 25.55 gigaflops/watt.

The number one system in the Green500, a ranking of supercomputer efficiency, was MN-3 from Preferred Networks in Japan, which uses the MN-Core chip, an accelerator optimized for matrix arithmetic, as well as an Intel Xeon Platinum 8260M processor. MN-3 achieved a 29.70 gigaflops/watt power-efficiency and has a TOP500 ranking of 337.

Intel will integrate HBM in the next generation of its Intel Xeon Scalable processors (Sapphire Rapids). Optimized for HPC and AI workloads, it will increase I/O bandwidth with PCIe 5.0 and Compute Express Link (CXL) 1.1 support and add a built-in AI acceleration engine. The company also said it is in the process of system validation for its Xe-HPC-based GPU.

Nvidia expanded its HGX supercomputing platform, which is focused on industrial AI and HPC workloads. The company added the A100 80GB PCIe Tensor Core GPU, which provides 2TB/s bandwidth and provide 80GB of HBM2e high-bandwidth memory; Quantum-2 modular switches, which provide scalable port configurations up to 2,048 ports of NDR 400Gb/s InfiniBand with a total bidirectional throughput of 1.64 petabits per second; and Magnum IO GPUDirect Storage for direct memory access between GPU memory and storage.

Rigetti Computing is launching a multi-chip quantum processor. The company said its modular approach, which connects multiple identical dies into a large-scale quantum processor, solves scaling challenges for fault-tolerant quantum computers and reduces manufacturing complexity. It plans to make an 80-qubit system powered by the processor available this year.

Memory
Weebit Nano announced commercial integration of an oxide-based ReRAM (OxRAM) cell with an ovonic threshold switching (OTS) selector. The company said this is a critical step in its commercialization path for the discrete (stand-alone) memory market and will enable the implementation of 3D memory stacking and crossbar architectures in future developments.

Power
Infineon introduced the 650 V TRENCHSTOP 5 WR6 family of IBGT discretes in the TO-247-3-HCC (high creepage and clearance) package. It covers 20 A, 30 A, 40 A, 50 A, 60 A and 70 A current ratings and targets power factor correction (PFC) for residential and commercial air conditioning systems as well as welding applications.