Week In Review: Design, Low Power

Tools & IP
Synopsys introduced its DesignWare USB4 IP solution consisting of controllers, routers, PHYs, and verification IP. It supports USB4, DisplayPort with HDCP 2.3 security, PCI Express, and Thunderbolt 3 connectivity protocols through USB Type-C connectors and cables. The USB4 IP operates at up to 40 Gbps, twice the maximum data rate of USB 3.2, and is backwards compatible with USB 3.x and USB 2.0 systems. A successful test chip tapeout of the USB4 IP has been done in an advanced 5nm FinFET.

Imagination Technologies launched iEW400 Wi-Fi IP. Based on IEEE 802.11ax/Wi-Fi 6, the IP provides integrated RF and baseband for low-power and battery-powered applications such as IoT, wearables, and hearables. It offers 20/40MHz operation for power conservation on low-data-rate applications, Target Wake Time for deep-sleep periods, OFDMA for bandwidth segmentation, Basic Service Set Coloring for dense environments, dual sub-carrier modulation, and an optional upper MAC and power management unit.

Codasip’s SweRV Support Package has been extended to include the open source, RISC-V-based SweRV Core EH2 and EL2 that were contributed to CHIPS Alliance by Western Digital. These have been added to the support already released for the SweRV Core EH1. The Support Package provides tools and components needed to design, implement, test, and write software for a SweRV Core-based SoC. In addition to the commercial Pro version, a Free version is available for the educational market.

UltraSoC debuted a new solution that provides system-level analytics, optimization and debug capabilities at speeds of 10Gbps over USB, making it accessible even in a closed chassis. The USB 2.0 IP is based on a patented hardware-based bare-metal technology that requires no software running to establish communication. Combined with high speed USB 3.1 IP from Synopsys, it can gather high volumes of rich system performance data, with access from “cycle zero” on start-up. eUSB is also supported for access to devices designed on advanced process nodes.

SmartDV launched a series of series of video, imaging and entertainment system Design IP compliant with a variety of standard protocol specifications. The new IPs cover: V-by-One, a high-speed serial video interface for HDTV; VESA DSC, a video compression and decompression standard; HDCP 2.3, used for copyright-protected media; HDMI CEC for remote control; HDMI eARC (enhanced Audio Return Channel), an HDMI feature that enables high-quality digital audio to be sent back from the TV via HDMI; CXP (CoaXpress), a high-speed imaging standard for serial transmission of video and still images; and SLVS-EC (Scalable Low Voltage Signaling with Embedded Clock), a high-speed serial interface scheme for image data transmission.

Green Hills Software debuted new software development tools targeting 32- and 64-bit RISC-V processor architectures. The tool suite is applicable for both pre-silicon and silicon platforms and comprises the MULTI integrated development environment, multicore debugger, optimizing C/C++ compilers, and hardware JTAG probe.

Efinix uncorked three software-defined SoCs based on RISC-V that are optimized for the company’s Trion family of FPGAs, from cost-sensitive to high performance. The SoCs are preconfigured with a RISC-V core, memory, a range of I/O and have interfaces for embedding user functions.

Standards
The MIPI Alliance completed development on MIPI A-PHY v1.0, a long-reach SerDes physical layer interface for automotive applications that spans an entire vehicle. It aims to be the foundation of an end-to-end system designed to simplify the integration of cameras, sensors and displays, while also incorporating functional safety and security. The specification is undergoing member review, with official adoption expected within the next 90 days.

Certifications
Synopsys’ Design Compiler NXT synthesis solution was qualified by Samsung Foundry for its 5/4nm FinFET process technologies. New optimizations for Design Compiler NXT include power-driven mapping and structuring techniques and concurrent clock and data (CCD) optimization.

Cadence’s digital full flow and custom/analog tool suites received DRM and SPICE certification for TSMC’s latest N6 and N5 process technologies. Optimizations to the digital tool suites include enhanced physical optimization and timing signoff closure, enhanced EUV layer support, a new chip integration checker for floorplan design rules, and additions to via pillar, autoNDR and advanced MIMCAP support. The analog tool suite added an accelerated custom placement and routing methodology, multiple patterning, density and electro migration requirements, and expanded design rule constraint support.

Synopsys’ DesignWare True Random Number Generator (TRNG) IP received validation by the National Institute of Standards and Technology (NIST) Cryptographic Algorithm Validation Program (CAVP). The validation will make it easier for customer end products to receive lower-risk Federal Information Processing Standards (FIPS) 140-3 certification.

Deals
Ambarella adopted Cadence’s Clarity 3D Solver for design of its next-generation AI vision processors. In a recent evaluation, an Ambarella computer vision SoC and PCB were run on the Clarity 3D Solver. In both cases, when there is no solid reference plane for high-speed signals, the Clarity 3D Solver identified the Ambarella design defects and correct scattering parameter (S-parameter) response. For both simulations, the Clarity 3D Solver took 29 hours to process the case with 202 ports running at 48 bits via a LPDDR4 interface on a geometrical combination of package and PCB layout design.

Baikal Electronics used Synopsys’ Fusion Design Platform and DesignWare IP solutions for its 28nm Baikal-M1000 processor-based SoC, which achieved first silicon success. The Baikal-M architecture consists of eight 64-bit Arm processors and an eight-core Arm GPU. The company cited faster implementation and energy efficiency.

SemiDrive is using Imagination Technologies’ PowerVR Series9XM GPU in its automotive smart cockpit chip, X9, which has been taped out and been brought up successfully. SemiDrive cited performance benefits and the isolation capability and security provided by hardware virtualization.

Events
Many conferences have now been cancelled, postposed, or moved online. Find out what’s happening with each at our events page. How about checking out a webinar instead? Or check out our latest video, which explains how to place macros inside a PHY in 7/5nm SoCs.

Ansys will host the Simulation World virtual conference on June 10 & 11. Focused on multiphysics simulation across many sectors, there will be a dedicated Semiconductor Track and several industry tracks devoted to 5G, industrial IoT, electrification, and autonomous vehicles.

The ESD Alliance will host its 2020 CEO Outlook as a virtual event on June 17 at 10:30 a.m. PST. This year’s panel features Arm’s Simon Segars, Joseph Sawicki of Mentor, OneSpin’s Raik Brinkmann, John Kibarian from PDF Solutions, Prakash Narain of Real Intent, and Silvaco’s Babak Taheri. The panelists will discuss the impact of COVID-19 on the industry, along with major new trends and potential opportunities.

DAC will be a virtual event this year. It will still take place July 19 – 23, 2020. More details on the new virtual format will be available at a later date.

Arm TechCon has been renamed Arm DevSummit and will be held virtually October 5-9, 2020. The call for papers and presentations is now open through June 9.

Upcoming Webinars
Mentor will address using machine learning to accelerate designs; Synopsys will dig into automated testbench creation to accelerate NoC verification; Rambus will explain GDDR6 and its application to AI and ADAS.