Chips.gov website launches; workarounds to U.S. sanctions; YMTC using local sources for 3D NAND; photonic debonding; Gelsinger at MIT.
The U.S. Commerce Department launched Chips.gov, a website that covers all aspects of the CHIPS Act, including funding opportunities and job openings. In similar vein, Intel CEO Pat Gelsinger focused on the future of semiconductor manufacturing in America in a talk at MIT. Intel has committed to expanding semiconductor manufacturing in the U.S., including spending an initial $20 billion on new fabs in Ohio and another $20 billion on fabrication plants in Arizona.
Meanwhile, equipment companies in Japan and the Netherlands are likely to find ways around U.S. sanctions, as Nikkei Asia reports. China’s Foreign Minister Qin Gang promised, “The blockade will only further stimulate China’s determination for independence and self-development.” And YMTC is making progress in producing advanced 3D NAND products with locally sourced equipment, per The South China Morning Post.
Continuing the tit-for-tat, the U.S. asked South Korea to urge its chipmakers not to fill any market gap in China if Beijing bans memory chipmaker Micron from selling chips, the Financial Times and Reuters reported. And Seagate has been fined $300 million for violating export restrictions on Huawei, according to the Wall Street Journal.
Eindhoven University of Technology (TU/e) signed a memorandum of understanding to jointly develop a 10-year strategic research roadmap in the fields of plasma physics, artificial intelligence, mechatronics, and semiconductor lithography. The TU/e and ASML will invest equally in the joint program, which will create up to 40 Ph.D. positions annually. In turn, ASML will supply its top engineers as hybrid teachers in these areas and will increase the number of internships it hosts.
SK Hynix said production cuts by memory chip makers will improve market conditions from the second half of 2023, after it reported a record operating loss for the first quarter. It also forecast that artificial intelligence applications will to drive an increase in memory chip revenue by 30% or more in the next five years, according to Reuters. The Wall Street Journal also recorded optimism by SK Hynix and Samsung, which say the market may be bottoming out.
Siemens’ Calibre nmPlatform tool for integrated circuit (IC) verification sign-off is now fully certified for TSMC’s advanced N3E and N2 processes. TSMC and Siemens also collaborated to certify Siemens’ mPower analog software for transistor-level electromigration and IR drop (EM/IR) sign-off for TSMC’s N3E process. Further, TSMC and Siemens are now collaborating to certify mPower digital software for TSMC’s N3E process.
Bosch plans to acquire TSI Semiconductors, including a 200mm fab based in Roseville, California. Bosch intends to invest more than $1.5 billion in the site to convert to state-of-the-art 200mm tooling for silicon carbide (SiC) device production in 2026.
KLA leased another Silicon Valley office building to keep up with “record growth.”
Argonne National Laboratory opened the Argonne Quantum Foundry to develop, test, and fabricate semiconductor qubits. It will also provide a U.S. supply chain of materials for both foundational science and industry research. The foundry also features a prototype silicon-based quantum computer. The data collected at the foundry will be used to build a national database of materials and their properties. A second foundry, focused on superconducting materials for quantum computing, will open soon at the SLAC National Accelerator Laboratory.
Japan will provide Rapidus an additional 260 billion yen ($1.94 billion), according to Nikkei Asia. The fresh round of assistance will be used to bolster the company’s R&D operations. Rapidus also began sending personnel to IBM’s research facility in New York.
State-owned Chinese resource developers are expanding production of rare-earth metals in response to higher government quotas, working to build a supply chain that can handle growing demand for electric vehicles and other high-tech products, Nikkei Asia reported.
Brewer Science and PulseForge will discuss photonic debonding at CS Mantech. The new technology uses high-intensity pulses of light in conjunction with a proprietary inorganic light-absorbing layer to debond temporarily bonded wafer pairs. Photonic debonding enables back-end-of-line processing of ultrathin wafers.
Synopsys strengthened its collaboration with TSMC and Ansys for multi-die system design and manufacturing. The Synopsys Multi-Die System Solution targets early architecture exploration, rapid software development and system validation, efficient die and package co-design, robust and secure die-to-die connectivity, and enhanced manufacturing and reliability.
Fraunhofer IIS EAS and Achronix are teaming up to build a multi-chip system composed of several chiplets and to validate performance and interoperability of chip-to-chip transaction layer interconnects such as Bunch of Wires (BoW) and Universal Chiplet Interconnect Express (UCIe). The project will create a demonstration platform suitable for applications such as 5G/6G wireless infrastructure, ADAS, and high-performance test and measurement equipment.
POET announced “POET Starlight,” a packaged light source solution for AI applications. POET has entered into an agreement with Celestial AI, creators of the Photonic Fabric, for development and production.
Teradyne was named by VETS Indexes as a Recognized Employer in the 2023 VETS Indexes Employer Awards. This award recognizes the organization’s commitment to recruiting, hiring, retaining, developing, and supporting military veterans.
Three unnamed technology companies will establish electronic semiconductor chip manufacturing plants in Jalisco and Baja California to meet worldwide demand, according to the head of the National Auto Parts Industry (INA) business chamber, Alberto Bustamante, Mexico News Daily reported.
2023 semiconductor equipment revenues are forecast to dip to $87 billion, down 13% year over year according to Yole Intelligence, part of the Yole Group. After three years of growth, the wafer fab equipment market is down 26% in 1Q 2023. “The decline is largely due to memory chipmakers pushing back or even canceling orders, despite long equipment lead times and high fab utilization rates,” said Taguhi Yeghoyan, senior technology and market analyst in Yole’s Semiconductor Equipment, Subsystems and Test Division.
Semiconductor revenues are forecast to decline by 11% in 2023 to $532 billion from 2022’s level of $600 billion according to Gartner. “An oversupply of chips is elevating inventories and reducing chip prices, accelerating the decline of the semiconductor market this year,” said Richard Gordon, Gartner’s practice vice president.
MIT engineers demonstrated a low-thermal-budget synthesis method (growth temperature < 300 °C, growth time ≤ 60 min) for monolayer MoS2 films. It would allow the integration of 2D materials directly onto a silicon circuit, which could lead to denser and more powerful chips.
Scientists at Tokyo Metropolitan University have successfully developed multi-layered in-plane transition metal dichalcogenide junctions, demonstrating their potential use in tunnel field-effect transistors (TFETs) for ultra-low power consumption in integrated circuits.
Further reading
Read about what data center chipmakers can learn from automotive, photonics testing, CD-SEMs measurements, and other issues in our latest Test, Measurement & Analytics Newsletter:
Check out a Special Report on Nanoimprinting and the recently issued CPO standards in our latest Manufacturing, Packaging & Materials newsletter:
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