Fewer manufacturers, higher costs, handling challenges and more defects make the transition difficult.
By Mark LaPedus
The most critical component in semiconductor manufacturing is arguably the silicon wafer, but the substrate is often taken for granted in the supply chain.
After all, silicon wafer makers have nearly perfected their craft over the years and produce what many consider mere commodities. And on the business front, silicon wafer makers often find themselves with excess capacity and low margins in both boom and bust cycles.
With those trends in mind, the transition toward the next-generation 450mm wafer size likely will be a long and painful chapter for silicon wafer suppliers. If the transition isn’t enough to deal with, there is a push for new 450mm wafer standards, including the re-emergence of a “notchless” technology and a tighter edge-exclusion specification. The two standards promise to provide more processing area on a 450mm wafer.
In addition, the sizable investments required for 450mm, coupled by the questionable lack of return, are causing some silicon wafer manufacturers to rethink their efforts in this arena. Today, the five largest silicon wafer makers in order are Shin‐Etsu Handotai (SEH), Sumco, Wacker, LG Siltron, and SunEdison (formerly MEMC).
To date, Sumco is the only vendor making and shipping 450mm silicon wafers, mainly for R&D purposes. And only two suppliers, SEH and Sumco, have made a commitment to invest in 450mm silicon wafer production over the long haul, said Richard Winegarner, a principal at Sage Concepts, a research firm. “Wacker doesn’t want to be a pioneer (in 450mm). They may participate later on,” Winegarner said. “SunEdison doesn’t have the money for 450mm, nor are they interested in it.”
It is unlikely that LG Siltron will invest in 450mm. Simply put, the market is not big enough to justify four or five 450mm silicon wafer suppliers, as only a handful of chipmakers are expected to build 450mm fabs. In total, a silicon wafer maker must invest at least $1 billion to develop and build 450mm capacity, compared to roughly $600 million to $800 million for 300mm, Winegarner said. “450mm might be cost effective,” he said, “but will it ever justify the investment?”
On the hot seat
Generally, silicon wafer makers have been under the radar. That changed on March 11, 2011, when Japan was struck by a deadly earthquake and tsunami. The “Great East Japan Earthquake” caused considerable damage in Japan, and it also hit the worldwide IC supply chain. For example, SEH’s Shirakawa Plant in Japan was hit by the quake and was out of action for some time. The plant produces a large share of the world’s 300mm silicon wafers. When the factory went down, chipmakers went into a panic-buying mode for 300mm silicon wafers. “That kept silicon wafer prices tight in 2011,” Sage’s Winegarner said.
In 2012, SEH moved to regain lost share by cutting their prices. Others followed suit, causing price pressure in the market. Last year, silicon wafer area shipments were flat, but worldwide sales fell from $9.9 billion in 2011 to $8.1 billion in 2012, an 18% decrease, he said.
So far in 2013, silicon wafer prices are depressed. And amid lackluster demand, SEH and Sumco separately are undertaking an expensive effort to develop 450mm silicon wafer technology, which will present some new challenges. In the general silicon wafer production process, a cylindrical ingot of monocrystalline material is formed by pulling a seed crystal from a melt. The ingot is then sliced with a saw and polished to form silicon wafers.
A crucible to make 300mm wafers is 32 inches in diameter, compared to 40 to 44 inches for 450mm. The height of a 450mm ingot is 10 feet, which is the height of a basketball hoop. Compared to 300mm, it will take twice as long to grow 450mm crystals and two to four times longer to cool them, according to Sumco.
A 300mm wafer weighs 128 grams, with a standard thickness of 775μm. A 450mm wafer weighs 340 grams, with a thickness of 925μm, plus or minus 20μm. The sheer size of the substrate may cause it to sag or warp when moving in a fab line. “The most challenging issue (for 450mm silicon wafers) is flatness,” said Hisashi Furuya, managing director and general manager of the Technology Division at Sumco. “Although the specification of a prime wafer has not been (determined) yet, we image it must be very tight.”
Currently, Sumco is part of a critical program to develop 450mm test wafers. In this program, Sumco ships 450mm silicon wafers to members of the Global 450mm Consortium (G450C). The wafers are then patterned using nanoimprint lithography and subsequently distributed to chipmakers and fab tool vendors for R&D purposes.
On average, there are about 31 defects on a 450mm wafer at 35nm geometries now, compared to around 66 defects at 38nm a year ago, according to data from the G450C. “We see a continuous quality improvement on 450mm wafers,” said Michael Goldstein, materials principal engineer in the Global Fab Materials unit at Intel. Goldstein is also part of a group that is overseeing the development of silicon wafers at the G450C.
To notch or not to notch
The G450C also is spearheading some new 450mm wafer standards, including a “notchless” technology. Going back in history, a 100mm (4-inch) wafer was not perfectly round, but rather it had “flats” cut into three sides of the wafer. A 150mm (6-inch) wafer had one or two flats. The flats were used to align the wafer to a particular fab tool.
Then, at 200mm, the industry decided to put a tiny notch, or “V groove,” on the side of a wafer for alignment purposes. In the alignment process, however, a tool would sometimes put too much stress on the notch, thereby damaging the symmetry of the wafer to one degree or another.
As a result, the industry proposed the idea of going “notchless” at the early stages of the 300mm transition in the late 1990s. Instead of a “V grove,” the wafer would have a “fiducial marker” or mark on the back. Using optical readers, the marker would dictate the alignment process for a fab tool.
The industry nixed the notchless approach in the early stages of 300mm. Instead, 300mm makes use of a notch for alignment purposes. Like 200mm, the notch also disturbs the symmetry of a 300mm wafer. “The notch has to be polished during production to eliminate stress,” Goldstein said.
Then, in 2007, Sematech floated the idea of using the notchless approach for 450mm wafers. Like the ill-fated 300mm proposal, a fiducial mark would be placed on the back of the wafer using a laser scribe. According to the G450C, the idea is to scribe greater than four fiducial marks on multiple locations of the wafer to boost the throughputs. The desired accuracy for the optical readers or cameras is 3σ = ± 0.5μm.
Today, the reaction is mixed over 450mm notchless wafers. “We do not know whether the effect would be worse or better compared with notch,” said Sumco’s Furuya. “It will strongly depend on the pattern and shape of the laser marks.”
Notchless has some major advantages for certain fab tools. “In some chamber technologies, the notch is very, very difficult to deal with,” said Kirk Hasserjian, corporate vice president for the Silicon Systems Group at Applied Materials. “A notchless wafer would enable us to have more of a symmetric way to get edge die yield.”
As a result, notchless is gaining steam. “This is a very good example of something that none of us would believe could see the light of day a year ago,” Hasserjian said. “What that will require is a lot of standardization.”
Presently, the G450C is looking at some 30 different types of fudicial marks from various entities, but the goal is to standardize on at least one. “We are looking at different marks and testing to see how readable they are,” Intel’s Goldstein said. “It has to be readable. Since you are building films, you have to make sure that they are not covering the mark. You have to be able to read through the entire process to align the wafers.”
The industry hopes to establish a notchless standard by next year. Meanwhile, in parallel, the industry also is working on another, and perhaps more difficult, edge-exclusion standard. “Each wafer has an edge area that is not considered usable,” Goldstein said. “In the past, it was a 3mm edge exclusion. Today, it is 2mm.”
In 450mm, the industry is proposing the idea of a 1.5mm edge exclusion, which will give chipmakers more usable area on the wafer “Closer to the edge, we need to have more uniformity for the wafer itself,” he said. “For that, we have to work with suppliers to make the wafer flatter. Edge exclusion is more of a challenge. You have to do a much better job of polishing the wafer, and to be more careful with the edge finish.”
Regarding the current and general state of 450mm silicon wafers, Goldstein said the industry is making steady progress. “Is it ready for what we need today? Yes. Is it ready for volume manufacturing? Not yet. The industry is progressing step-by-step,” he added.