Is the industry about to run out of analog designers, or will automation finally happen and increase their productivity?
The numbers being touted by the semiconductor industry for IoT edge devices are staggering. How they are going to be used, who will make them, or indeed who will make money from them are much less certain.
The industry seems to be clear about the content of these devices. A small processor, some flash memory or possibly even some of the new memory technologies that are coming along, a radio interface, and a bunch of sensors. Most of the digital content is fairly standard and likely to be released as sub-systems.
A recent example comes from ARM and TSMC, who announced a subsystem with ARM’s Cortex-M processor, an embedded flash controller and Cordio radio IP that they say will allow the integration of sensors and other peripherals. James McNiven, general manager for systems and software at ARM, said this “enables our partners to focus finite resources on the system functionality that differentiates them in their market.” It is the analog portion that provides that differentiation.
“IoT devices have just enough digital to get by but not enough to chew up the battery,” says Jeff Miller, product marketing manager at Tanner EDA by Mentor Graphics. “There are multiple analog pieces, MEMS (microphones, pressure sensors, accelerometers), the circuitry for any analog devices you want to read in or control, if it has actuators, and then the radio which looks more like analog than digital even though they do contain digital components. The biggest value comes from the analog circuitry.”
No disagreements from Wilbur Luo, senior group director for research and development at Cadence. “The digital piece is a state machine,” said Luo. “It may do some calibration and possibly offload some of the analog, but there will be critical mixed-signal portions of the design.”
But few have stopped to ask who will be doing all of the analog design necessary for these devices. Analog design has become the long pole for many chip designs, and if the analog content grows to become a significant percentage of the chips, with the digital prepackaged as a sub-system, design times for these devices will be dominated by analog.
At the same time, there is a desire to see cycle times reduced to a couple of months for these devices. Something has to change. “If the chip contains an accelerometer, for example,” says Miller, “this is probably designed from scratch. It makes sense that this is the long pole. It just has to be acceptably short.”
For this to work, the analog design cycle has to go through some significant change—maybe even automation. Perhaps there are other ways to speed up the development cycle, as well.
History shows that automation of analog has been unsuccessful. The advances in analog have been tiny increments to certain parts, but in general the automation of analog has failed. “In the past we attempted to apply our routing technology to analog circuits,” says Mark Williams, CEO of Pulsic. “We realized very quickly that it was never going to achieve the kinds of results that an analog designer would be able to produce. There are things that a seasoned analog designer would do to get the kinds of results that they needed.”
But some things may have to change. “Circuit designers have a floorplan in mind based on previous similar designs,” explains Luo. “They are looking for help with placement or routing. There is a lot of opportunity there if you have a good, solid placer and router. Historically, people have had problems with that because, while it may have met all of the DRC checks, it may not have been aesthetically pleasing. We have to convince the analog designers that less-pretty designs still work. This is a tough thing to overcome. If it meets the design spec and has been verified both manufacturability-wise and from a parametrics perspective, then they should be happy. They cannot continue to tune everything down to the sub-micron level.”
Degrees of automation
The industry is looking at automation from many different perspectives, ranging from full automation to flow improvements, verification improvements, raising the abstraction level and everything in between.
“I do not see a magic bullet in analog synthesis or automated layout,” says Miller. “High performance analog will remain black magic, full custom process for the foreseeable future. There are ways that we can make that faster without fundamentally changing the way people work.”
But not everyone needs high performance, just good enough performance. “Analog designers are not looking for push-button automation,” says Amit Gupta, president and chief executive officer for Solido Design Automation. “They want control within the EDA tools. When you are getting your IP from a provider you are not doing full custom analog, instead just doing a small piece of differentiated design. The tools do need to mature to address a different kind of designer—not an expert analog designer, but more of an ASIC designer who may not know all of the details about an analog chip. 30% to 50% of power/performance/area is probably left on the table just using off-the-shelf IP rather than custom design.”
Can some of the tedium be removed from the process? “We are abstracting interactions with the design so that designers do not have to do as much manipulation,” says Fred Sendig, fellow within the analog/mixed-signal group of Synopsys. “You could view this as a learning system combined with symbolic editing and apply that to automation. There are other EDA companies that have explored push-button solutions, but for great analog designs, the engineer still has to get their hands in there. We automate, but let the designer manually intervene at any point, and then resume the automation. Assisted automation removes much of the pushback by analog designers, so we get better responses than prior automation attempts.”
Others believe they have found the magic bullet. “We analyzed what was happening and realized that a place and then route solution would not work,” says Williams. “It needed an entirely new way to look at the problem and we call it polymorphic layout. It looks at the analog circuit — the schematic — and derives the constraints from the topologies and netlist and then figures out what kind of layout needs to be applied. It does it all at once.”
Williams is not against the analog designers getting in and helping. “Layout guys may take the results and fine tune them, but if we can get them 90% to 95% of the way … they no longer have the timescales that they used to have and people are proactively looking for solutions.”
Sendig points out that there are 1,400 analog designers within Synopsys and so they have a huge incentive to increase productivity. “There used to be a fear that if you add automation, you will put the analog designers out of work. Not true. We allow the good designers to be really great and more productive.”
Digital design would not have progressed as much as it has without abstraction, but that relies on synthesis being available. Place and route is proving to be difficult enough for analog, but analog synthesis is barely a dream today. Still, there is a glimmer of hope. “People are moving up one level of abstraction, where instead of laying out transistors,they would consider differential pairs or current mirrors and use these as building blocks,” says Luo. “They can be pre-made and characterized, and then they can be placed and auto-routed.”
Sendig agrees: “Structured design takes the abstraction up one level and designers can use blocks as things that can be instantiated instead of placing every transistor. In some of the newer nodes, such as 14nm and 10nm, it just means metalizing the devices because you don’t want to deal with the local interconnect problems in transistors. How far you take structured design depends upon the methodology you are utilizing.”
But even here there are some naysayers. “It may leave some area on the table,” adds Sendig. “However, there are cases when this is not true because by being more efficient, the users can explore more design space and actually create better designs in the same timeframe.”
Streamlining the flow
But place and route is only one piece of the analog flow. “As tools vendors, there is a lot we can do to accelerate the process within the bounds of the traditional flow,” says Miller. “Our goal is to make it as easy and productive as possible and to remove barriers where we can.”
Luo provides an example of this type of improvement. “Electrically-aware design means that while doing layout you can extract parasitics and do EM analysis – instead of three separate steps. This shortens the design cycle and gives the layout and circuit designers access to electrical information.”
Verification takes a lot of time. “One of the challenges is how to reduce the number of SPICE simulations that you have to perform while maintaining full design coverage for various types of corner analysis,” says Solido’s Gupta.
He sees two major trends that are affecting verification. “Moving to smaller process nodes creates more physical variation and thus needing to verify the designs across these wider variations.” The second trend is specific to IoT and wearables. “We are seeing ultra-low power becoming dominant where the voltage source is lower and the margins are a lot less.”
“Testbench reuse has been a big item on the digital side,” points out Luo. “It is starting to become a bigger thing for mixed-signal. UVM and metric-driven verification have migrated over to mixed-signal. Now we have reusable testbench components and assertions placed inside the testbench that monitor things. Many companies will produce families of IoT devices, so that enables a lot of reuse. There will be verification components based on wireless standards — Zigbee or 802.11. You will have standards based stimulus generator and monitors making sure the protocols are right.”
Luo notes that analog developers have been “SPICE jockeys,” and the concept of moving from simulation to verification is going to be new for the custom designers and it will be a big area for productivity improvement.
Another concept that provided a huge boost to digital productivity was the IP model. “Analog IP is often hard IP,” says Sendig. “You have things like data converters and sensors. There is a clear spec about how to connect to it. If it is not differentiated, then just buy it. Why bother hardening it yourself? If it does matter and you want a differentiated circuit then you have to design and implement it.”
Another interesting product introduction has been the custom analog and mixed-signal EDA development platform by Invionics Inc.. “This is directly in response to customer pressure,” said Brad Quinton, chief executive officer for Invionics. “We now have a complete API for Verilog-AMS that will enable user to find and modify design elements and connectivity. Analog is more specialized, less mainstream and thus less supported by standard products.”
Analog design at the latest nodes presents additional challenges, but most IoT designs will remain on larger process nodes. “Foundries are putting new flavors of their processes together for ultra-low power intended for IoT and wearable applications—65nm low power, 40nm low power and also 28nm,” explains Gupta. “At the recent TSMC conference they also announced 16nm LP also geared for IoT and wearable.”
According to Simon Wang, senior director of IoT business development at TSMC, it’s likely that in the near term such IoT devices will be fabricated in 55nm and 40nm process technology.
“Analog has become a problem in cell phones because they are chasing the leading edge process technologies where analog becomes progressively more difficult – way more so than digital,” points out Miller. “For IoT, they can choose the process nodes that are more conducive to analog design because of the smaller digital content. We see a lot of analog designs starting at 90nm, 130nm, 180nm.”
Many designers are staying on older nodes because performance meets their needs, but there could be other hidden reasons. “In some cases they would go to the next process node if it were easier to do so,” Williams argues. “28nm is complex to do by hand and so few analog suppliers offer it. At 40nm, it is more manageable, but productivity is still a huge benefit here.”
Others are not swayed by this argument. “It is not just productivity that is keeping them at the older nodes, it is often the process costs,” says Sendig.
The big winners
At this point it is not clear if the sensor designers will want to integrate the rest of the circuitry and make complete IoT devices, or if they will license their IP to others for integration. “Most of the entrants at the moment are existing IP companies who are adding IoT capabilities into their flow,” observes Gupta. “We have not yet seen any new companies formed just targeting IoT.”
Mojy Chian, chief executive officer for Silicon Cloud sees it differently. “A lot of IoT design companies are system companies and they do not have a lot of chip design knowledge. They are putting the system together using discrete components. But they will quickly realize that this solution is not cost effective and doesn’t have the power or footprint desired. Integrating them becomes important, and we will see a lot of this happening.”
Miller believes it will be up to the large semiconductor companies putting together the chips and selling them to integration companies to put together a final product. “In the long run there is a lot of pressure on these things related to cost, size, power consumption, and they will push the industry toward higher levels of integration. They will be designed as off-the-shelf parts that IoT end-user companies can use.”
Miller also observes that “the sensors are the magic sauce today, and there is a boundary between them and the device makers. The know-how to make the sensors is so specialized that it behooves them to make and sell the parts rather than the end device.”
But what is in store for the analog designers? They are most certainly a finite resource and one that appears to be in hot demand. Many of them have gained their experience through hard and bitter experience. “The pipeline of analog specialists is already scarce, and will be exacerbated if IoT takes off,” concludes Miller.