Extending UPF For Use In System-Level Design

Energy efficiency as a design constraint continues to dominate, and now that we see greater momentum behind a shift left toward system-level design, we are naturally seeing power-aware system-level design as a key area for EDA and IP enablement, especially among mobile and IoT platform providers. In my last article I highlighted the role that IP power models play in the architecture and design ... » read more

Low Power Trends Toward FinFET

My previous blog, Power Reduction Techniques, covered which low power techniques were applicable for various process nodes, from larger planar CMOS process technologies through finFET. The 16 and 14nm finFET-based process nodes are moving into production this year, and we are seeing many companies rapidly move their designs to finFET. In my last post, I noted some of the reasons why finFET is s... » read more

Image Sensor And Display Enhancements Drive Low-Cost Smartphone Growth

The low-cost smartphone segment is fueling the growth of the overall smartphone market. Smartphones are being adopted in emerging markets and are displacing feature or basic phones in developed markets. Mobile phone device manufacturers are closing the leadership gap with the No. 1 vendor – Samsung – by competing in both the high-end and low-end smartphone segments. See Table 1. Table ... » read more

IP Power Models Enable Energy-Aware System-Level Design

Energy efficiency is one of the primary design metrics for heterogeneous multi-core mobile platforms, and the very real threat of dark silicon reinforces the fact that we must manage energy consumption in these platforms intelligently. The way in which a platform is used absolutely determines how much energy it consumes, so we need to take a holistic approach to energy management. Furthermo... » read more

Using Multicore Processors To Accelerate Your High-Performance Embedded Linux Applications

The adoption of Linux is accelerating, as it is becoming the operating system of choice for a variety of embedded applications. However, designers of these performance-intensive, embedded SoCs running Linux or other virtual-memory operating systems are challenged with increasing performance requirements within constant or shrinking power budgets. Most processors either achieve the performance g... » read more

Memory VIP

As the consumer market, and the mobile segment in particular, continues to demand more features and more performance in their gadgets, the designer community is confronted with myriad challenges of delivering on those demands – not the least of which is verifying compliance of ever-evolving protocols that enable the connection of everything within the system on chip (SoC), and the connection ... » read more

Advances In Power Management For Physical IP In 28nm And FinFET Process Nodes

Engineering techniques to reduce power consumption by lowering the supply voltage and slowing the clock speed have reached practical limits of the semiconductor technologies. Newer solutions, which not only reduce power but also actively manage the power during the course of the SoC (system on chip) activity, are emerging. This article describes these innovations from the foundation intellectua... » read more

Power Reduction Techniques

As 16nm and 14nm finFET process nodes come into production toward the end of this year, the performance (up to 30% vs. 28nm planar CMOS), power (~30%) and area (up to ~50%) benefits have been well documented. The same can be said for the 28nm FD-SOI process as it gains more traction in the marketplace touting similar performance and power improvements as those for FinFET when compared against i... » read more

Using PCI Express L1 Sub-states To Minimize Power Consumption In Advanced Process Nodes

The major sources of Internet traffic are shifting from wired to wireless and mobile devices. With the growing regulatory requirements and increased consumer pressure for more power-efficient products, designers need to better understand and optimize the power consumption of battery-operated devices. Power consumption of a portable device widely varies based on the user’s behavior and appl... » read more

Rethinking Low Power Verification: LP + CDC Verification

In my last posting, we discussed some of the barriers that companies face in seeking to meet their low power verification objectives, and how the complete and integrated technologies in Synopsys’ new Verification Compiler product can help. This time, I’d like to introduce a relevant example of how unified technology solutions can help address complex design interactions in low power verific... » read more

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