Stop Getting Burned By Power Consumption Surprises

Very rarely these days do we get silicon back and find that we have missed our timing or test constraints by a significant margin. We have robust EDA tools, libraries and design methodologies in place to ensure that we can cleanly signoff against these constraints. However, we do continue to see too many unfortunate “surprises” in silicon related power (energy) consumption and thermal issue... » read more

Outbound Power Management

Many years ago when I first suggested that we should do platform-level power instead of focusing on the CPU, I was considered somewhat of a heretic. Yet, within 10 to 15 years of that recommendation, most of the platforms around us have moved to that method using operating system functions to keep track of the overall power, battery life, etc. As we move into the era of billions of connected de... » read more

Shift In Focus For Low Power Design

The increased levels of interest we have seen over the last couple of years in system-level power modeling and energy-aware system-level design methodology, coupled with broad participation in the associated industry standard activities around system level power, gives us a clear indication that a shift in focus for low-power design is taking place. Our attempts to deliver energy-efficient high... » read more

Using Automotive-Ready IP To Accelerate SoC Development

IP suppliers play a key role in the automotive supply chain to enable high-performance advanced driver assistance system (ADAS) SoCs. Vision-based SoCs may contain a high amount of third-party IP to implement the key embedded vision, sensor fusion, multimedia, security and advanced connectivity functions. And while IP suppliers have permeated the semiconductor ecosystem for consumer, mobile, PC... » read more

Interface IP Subsystems Speed TTM

Interface protocol specifications start out simply, handling off-chip communication for SoCs. As more companies get involved in the specifications, each company adds features to address their market segments. Each new version of the protocol specification offers new features and increased speed, and the protocols are often overhauled to work at higher speeds and improve performance for applicat... » read more

Confidence Is The New Verification

Everywhere around us the devices we use are getting connected to each other digitally. New devices that sense and quantify the parameters we need to make decisions are also being created. It is estimated that 26 billion connected devices will be installed by 2020, or roughly four per person on the planet! The whole purpose of the connected device is to observe/report and control remotely, of... » read more

One PHY Does Not Fit All

Consumers expect their battery-operated mobile devices to be faster, smaller and more reliable while providing greater functionality at a reduced cost. Most of all, consumers demand longer battery life and 24/7 access to data. To meet these demands, consumer system-on-a-chip (SoC) designers must make tradeoffs between features, performance, power and cost. Enterprise SoC designers have their... » read more

Securing 4K Content And Beyond Over HDMI

By Angela Raucher & Dana Neustadter As we move into the era of transmitting and receiving 4K Ultra-High Definition (UHD), High Dynamic Range (HDR) and even 8K UHD content, robust security becomes even more important for the protection of premium content. Today, High-Definition Multimedia Interface (HDMI) is the most widely used, and sometimes the only interface to connect high-resolution c... » read more

Extending UPF For Use In System-Level Design

Energy efficiency as a design constraint continues to dominate, and now that we see greater momentum behind a shift left toward system-level design, we are naturally seeing power-aware system-level design as a key area for EDA and IP enablement, especially among mobile and IoT platform providers. In my last article I highlighted the role that IP power models play in the architecture and design ... » read more

Low Power Trends Toward FinFET

My previous blog, Power Reduction Techniques, covered which low power techniques were applicable for various process nodes, from larger planar CMOS process technologies through finFET. The 16 and 14nm finFET-based process nodes are moving into production this year, and we are seeing many companies rapidly move their designs to finFET. In my last post, I noted some of the reasons why finFET is s... » read more

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