Early Power Modeling Using SystemC And TSMC System-PPA

How to make good power decisions when there isn’t enough information.


Power consumption is often more important than performance in today’s SoC designs because of battery size and power dissipation limitations. The dilemma is that the most leverage available to optimize power consumption is at the architectural design stage, but there often is not enough information available early enough to make accurate power decisions.

On the performance side, SystemC modeling at various levels of abstraction has become an industry-standard way to validate performance metrics like bandwidth, latency, and quality of service prior to emitting the final RTL. In fact, simulation and modeling capabilities are often built into IP products, like with the FlexNoC interconnect IP FlexExplorer simulation features. Design teams have attempted to use the same infrastructure and stimuli for power estimation as they have for performance analysis and tuning, but until recently the methodology has not been easy to implement. There are three reasons for this:

1. Any power analysis methodology is only as accurate as the baseline “real world” power measurements used to estimate system level power. To determine system power at the ESL level a look-up table (LUT) usually is created, where the power consumption of individual hardware functions running at various states is logged in a database. When the simulation runs and stimuli cause a hardware function to activate, its power consumption is looked up in the database and logged. In effect, system-level simulation integrates each power consuming activity over time, thereby creating an estimate of power consumption during an entire use case. Rather than actual power measurements of a hardware IP function executing a use case, we are often forced to estimate the power consumption numbers for use in the LUT based on process parameters and gate count. Ideally, we would like to be able to obtain data from a real chip running the IP function in a real manufacturing process at multiple voltage and frequency states. Using these measurements in the look-up table rather than mere estimates ensures our starting point for power analysis is more accurate, and therefore more useful for design teams to make decisions earlier.

Figure 1. Power state models are created at various levels of detail, which are determined by the metrics of interest, abstraction levels of available models, and acceptable length of simulation runtimes.

Figure 1. Power state models are created at various levels of detail, which are determined by the metrics of interest, abstraction levels of available models, and acceptable length of simulation runtimes.

2. There is no simple way to map individual IP function power consumption at a particular power state to its activity as a simulation is running a use case. We need an infrastructure that allows us to instrument or wrap the IP TLM models to log activity. In essence, the infrastructure must probe or “spy” on the running simulation to obtain the activity data, which is then mapped to the power database/ LUT. Having an easy-to-use and open means for this makes it easier for design teams to instrument larger, more realistic, and therefore more useful, design simulations for power analysis.

3. Leveraging our use of the power analysis data once we have obtained it isn’t easy. As stated before, SystemC simulation has been used extensively in the hardware design world for performance validation. The challenge now is to integrate power analysis data with the existing performance metric views (bandwidth, latency, etc.) in our analysis tools to make it easy for engineers to make tradeoffs between performance and the use of their power budget. This requires the means to easily integrate power analysis data with existing performance analysis and simulations platforms like Synopsys Platform Architect MCO and ARM SoC Designer.


Figure 2. SystemC models of a design are wrapped with instrumentation to extract activity data to be used for power analysis.

The good news is that TSMC has developed a new ESL power modeling methodology called System-PPA that promises to address all three of these barriers to adoption for early power analysis. To do this, TSMC created power databases/LUTs for their most popular technology libraries. This data was extracted from real chips designed with commercial IP at various PVT conditions. With a TSMC-provided TLM 2.0 wrapper template, design teams or IP providers can easily instrument their existing SystemC TLM models to extract the activity information that then gets correlated with the power database LUT. Currently, users have to manually create their power state APIs and integrate the resulting power consumption information into their existing analysis environments. But these activities will become more automated over time.

TSMC’s System-PPA methodology promises to be a key enabler for earlier system-level power analysis because it provides accurate power consumption data, eases the activity tracking and mapping processes, and provides data that can be integrated into and explored with existing analysis tools. All of this combines to create a methodology that will enable semiconductor design teams to more easily and accurately optimize their designs for power earlier in the design process.