Advanced packaging is creating new stresses and contributing to reliability issues.
While integrated circuit manufacturers have worried about electromigration for a long time, until recently most of their concerns have focused on the on-chip interconnects. The larger dimensions found in integrated circuit packages have, in most cases, improved heat dissipation, reduced current density, and eliminated most electromigration risks.
Over the last several years, however, the need to reduce device footprint in the face of slower die scaling has driven further package miniaturization. At the same time, increased use of semiconductors in uncontrolled environments, from smartphones to IoT sensors, has made heat dissipation more challenging. For solder bumps and TSVs, as for on-chip interconnects, the story is familiar—as manufacturers squeeze more circuit elements into less area, current density and temperature go up while heat dissipation becomes more difficult. Temperature and current density are major drivers for electromigration. Increasing them raises the risk of device failures.
Impact of solder metallurgy
However, solder metallurgy is substantially more complex than on-chip interconnect or package interposer metallurgy. The solder bump itself is an alloy of either tin and lead or tin and varying amounts of silver. In most cases, the bump connects a copper trace to either the interposer or the circuit board. Nickel-based under-bump metallization prevents reactions between the copper and the solder.
Current flowing through the solder bump causes joule heating. Heat from other parts of the package may also be dissipated through the solder bumps. As Sung-Su Ha and colleagues at Samsung reported, excessive heat can cause the formation of intermetallic compounds at the interface between the solder bump and the under-bump metallization. Because these compounds are likely to increase the electrical resistance at that location, still more heating will occur, potentially leading to thermal runaway.
Silver-tin solders have a higher activation energy for electromigration than lead-tin solders, as silver helps to stabilize the tin microstructure. Indeed, Ha said, 2.3% silver in tin gives up to four times the time to failure (T^50, the time when 50% of samples have failed) of solder with only 1.8% silver.
From fat bumps to thin wires
In on-chip interconnects, the current density is generally constant within a single line or a metal layer, thanks to the highly uniform line dimensions. The electromigration limit of the line is somewhat predictable and can be accounted for at the design stage. In packages, however, abrupt changes in metal composition and current density occur along the current path. For example, as current flows between a copper trace and a solder bump, it encounters a sharp change in electrical resistance and “current crowding” at the relatively narrow junction point. The thickness and even the shape of the contact pad can contribute to an increased risk of failure at that point. For example, in simulations reported at the 2014 Electronics System-Integration Technology Conference, Yi Li and colleagues found that octagonal contact pads minimized current density and temperature, probably by allowing a more uniform distribution of carriers through the volume of the solder bump.
Simulations are critical in studies like this. Test structures do not replicate the complex current flows actually seen by solder bumps in production devices. Shiguo (Richard) Rao at Vitesse Semiconductor found that real world FCBGA devices can have double the failure rates predicted by test structures. On the other hand, variations in bump size, underfill distribution, in the reflow process and in package warpage can all affect failure rates. As package miniaturization continues to increase solder bump and line density, seemingly trivial factors will become increasingly important to device performance.
Packaging customers are likely to demand more stringent process control.