Experts At The Table: Yield And Reliability Issues With Integrating IP

popularity

Last of three parts: The rising cost of shrinking features has prompted alternative approaches, but so far the industry is in limbo; business issues become more complicated when it comes to 2.5D and moving from one process node to the next.

Semiconductor Engineering sat down to discuss the impact of integrating IP in complex SoCs with Juan Rey, senior director of engineering at Mentor Graphics; Kevin Yee, product marketing director for Cadence’s SoC Realization Group; and Mike Gianfagna, vice president of marketing at eSilicon. What follows are excerpts of that conversation.

SE: As an industry we’ve got a pretty good grasp of what’s required at 16/14nm. When we get to 10nm we’re looking at new materials, quantum effect and enormous integration issues. What’s required to get to the next stage?

Gianfagna: There’s a fundamental shift here. Back at 90nm there was a shrink with scaling. Now it’s not about scaling. It’s a redesign. There are fundamentally different effects. There are temperature inversions where it gets faster the hotter it gets and slower the colder it gets. This is counterintuitive. So you don’t really scale and shrink anymore. You redesign a function at a process node, and moving to the next node becomes harder. The IP doesn’t just move over. You might not even want the same building blocks at 10nm as at 20nm. It’s not just the ridiculous cost of the fab. It’s the retooling of the entire supply chain. There is a lot of design data you re-use, but you’re not scaling the physical stuff. You’re re-doing it.

Yee: Everything is not a shrink or a redesign. With interposer technology you’re going to see different processes in the same package. You don’t have to have everything at 16nm or 10nm. You might do your application processor at the latest process and run everything else through an interposer. That will happen over time. It’s not just for IP, either. It’s a lot of work for companies to develop their own technology at the latest nodes.

SE: Does IP designed for a planar chip work in 2.5D, or does it have to be designed in 2.5D first for inclusion in other 2.5D chips?

Gianfagna: Clearly it’s the latter. You don’t take IP designed for a monolithic planar chip and plunk it on a substrate. That’s doomed to failure. You’re not going off chip. You don’t need the drive. You don’t need a lot of things. You don’t need ESD. By and large interposers are delivering silicon-level interconnect, not off-chip-level interconnect. They’re very different. You need to design that block with that application in mind. However, it is promising. We’re putting a lot of effort into 2.5D and 3D because that’s a way to expand your customer base and expand access to silicon. If the only way to get there is with 10nm, you can count the number of companies that can do that on two hands. I don’t believe that will be the future. The more than Moore stuff is the way because you can mix and match technology nodes. You can take silicon-proven known-good slices and use them in different ways.

Rey: Promises, promises. The promise of being able to use heterogeneous technology and integrate it through 2.5D is a very compelling proposition on paper. But the issue is that no one has brought the cost to a level where the technology can be proven. Now it’s coming down to a more realistic level. The technology has huge potential. We keep putting a lot of effort into it, but it’s still not measuring up to the initial predictions.

SE: But we are starting to see fanouts, which are almost there.

Rey: Right, there are some technologies. There was a speech in Grenoble last year where a company said that 3D technology will be critical for them. There are very well defined areas where it’s happening. But for most companies it isn’t happening yet. It’s a compelling proposition where you can have your logic in one process and your memory in another one and put everything through a silicon interposer, but it’s still not happening at the rate we thought it would.

Yee: I see 2.5D moving along at a faster clip than people give it credit. As with any new technology it’s going to come in phases or stages, and obviously with 2.5D you need to marry it with more memory. With new technology coming in there, we’re seeing a lot of activity in doing interposers and making sure it works with interposers. Once that’s proven it should ramp very quickly and get leveraged into other things.

Gianfagna: I hope that’s the case, because it’s been very close for quite awhile.

Yee: But if you go to a lot of shows now, you see real examples. It’s not in full force yet, but we’re getting closer to that promise.

Rey: We do a lot of development and we know people are using our tools for these projects. But we certainly thought it was going to happen faster than it did.

SE: Isn’t that the same for 16/14nm? People were predicting faster adoption.

Gianfagna: A lot of things are taking longer than predicted. It’s easy to get the month right. It’s hard to get the year right.

SE: The business model has to be realigned around 2.5D, though, too. It may be more money for certain groups within companies while the total cost may be less. That requires buy-in from the CEO and CFO, right?

Gianfagna: Yes, it is a different business model. But the business issues are a bigger challenge than the technology. Who takes the yield risk? Who assembles the final part? The stakes are higher in 3D, but it’s the same problem. Even at 2.5D someone is making the interposer. One vendor might be making the memory stack while a different one is making the processor. And you have high-speed SerDes stuff from a different company. You might have three or four vendors. Someone needs to take all the known good die and then strap on the assembly and yield risks. We see that as an opportunity. But do we have a robust supply chain doing this everyday? No. It’s brand new. And new means more delay in getting it right.

SE: Is it harder to get yield?

Gianfagna: It’s more the assembly. It’s the interface between the back side bumps and the bonding to the interposer and interposer stress. These are things we don’t understand yet. And 3D gets way worse because you’re dealing with a stack of paper-thin chips with big holes punched in them.

Rey: It will take time.

SE: Isn’t yield supposed to be theoretically better than 14nm? It certainly has been for homogeneous 2.5D chips such as Xilinx FPGAs.

Gianfagna: Yes, and that’s the point. But with a heterogeneous system, it’s not that simple.

Rey: The issue is what will be the yield of the whole part, not just the component. There are arguments in both directions. On one hand, you’re going with a smaller die and that will have better yield. And you have components that are well tested in older nodes. On the other hand, you have to integrate everything.

Yee: Once it gets mature and the cost goes down, so everyone is doing it, they’ll figure out how to get the yield up. If people don’t take the chance to try it, then it will disappear. But if enough people try it, then it will happen. They’ll figure out how to get the yield up.

Rey: It has been a cost issue, and costs have dropped to the point where it makes sense.

Yee: On the other side, which is the IP, with 2.5D it enables adoption of new standards. If you look at memory with HBM, you can’t do that without an interposer. Instead of going narrow and fast they’ve gone wide, and you can’t do that on a chip any other way. If that’s the direction the industry will move, you need 2.5D.

Gianfagna: It makes the whole IP market healthier.




Related Stories:



  • chipmonk

    Silicon Valley has rather low expertise in Packaging issues and that includes the EDA Co.s too. When it comes to the current generation of Packaging technology i,e. Flip Chip, the Fabless wonders pretty much rode the coat-tails of Intel / Motorola ( who developed it at their Labs in Phoenix, AZ ) and got the technology free via the OSATs. Not understanding the fundamentals, as this discussion among these ersatz “experts” sorely reveals, is the main reason why there is so much thrashing about 3-d and 2.5-d. And this time around Intel is not helping out because they can still afford to build Fabs where the integration can be done all on a single chip at high yield.