This year’s program is stacking up to be an insightful and educational four days.
If you’re asked “Do you know the way to San Jose?” in the next few days, chances are it’s a newbie to DVCon. Everyone else in chip design verification knows the way to the annual Design and Verification Conference and Exhibition about to convene at the San Jose DoubleTree Hotel.
This year’s program is stacking up to be an insightful and educational four days of tutorials, paper sessions, two panels, best papers and poster sessions and a keynote from Cadence’s Anirudh Devgan titled, “Tomorrow’s Verification Today.” A highlight will be the special session from Harry Foster of Mentor Graphics on “Trends in Functional Verification: A 2016 Industry Study” Tuesday, February 28, at 10:30 a.m. According to the description, the findings provide invaluable insight into the state of today’s electronics industry.
Formal verification users will have a chance to hear actual formal case studies from industry heavy hitters AMD, ARM, Cypress Semiconductor and Intel Wednesday from 10 a.m. until noon. Later in the day, a paper session will look at formal verification applications from Intel, MediaTek and Mentor Graphics. That session will be held from 3 p.m. until 4:30 p.m.
Of course, everyone looks forward to the exhibit floor, which opens Monday at 5 p.m. with the DVCon Expo and Booth Crawl. Refreshments will be available as attendees network and wander among the 31 exhibitors’ booths, including OneSpin in Booth #701.
Directly following the Booth Crawl is an event we’re thrilled to host with the ESD Alliance, “Ride with the Verify Seven,” a panel discussion hosted by Jim Hogan of Vista Ventures featuring next-gen verification leaders. They will be ready to talk about EDA, technology and, most important, making it in today’s environment, all relevant and topical subjects to the chip design verification community.
We’ll have drinks, snacks and plenty of opportunity to mingle with the panelists:
For more information on the evening, go to: http://bit.ly/2kNWx6T
The exhibit floor reopens Tuesday from 2:30 p.m. until 6 p.m. with the DVCon reception between 5 p.m. and 6 p.m. On Wednesday hours are the same for the exhibit floor and reception.
While the official DVCon program doesn’t include all that much on formal verification, the exhibit floor will. An offering of comprehensive demonstrations on some of the most popular formal applications and a few emerging trends, such as fault observation coverage, a production-worthy SystemC/C++ formal verification environment and equivalence checking for FPGAs. Safety critical analysis and diagnostic coverage have become hot applications for formal verification and will be demonstrated as well.
It’s all but guaranteed to be a week packed full of stimulating presentations, demonstrations and much more. Dust off a comfortable pair of shoes, download from iTunes Dionne Warwick signing “Do You Know the Way to San Jose?” and hum along as the chip design verification community gets set for another great conference.