Being able to meet increasingly stringent power budgets now requires checks at every step of the flow.
Signoff on power used to be a fairly simple check-the-box kind of activity. Even if power budgets weren’t exactly met, they could usually be fixed in future iterations of a chip, whether that involved derivatives or new revs of the same chip.
A number of things have changed since the much simpler days of 45/40nm and above, however.
More levels of signoff
One relatively new area for signoff involves RTL signoff, which is becoming much more important as the complexity of designs increases.
“Now we are dealing with multiple power domains, not just clock domain, possibly with dynamic frequency and voltage scaling (DVFS), huge numbers of operating modes, etc.,” said William Ruby, senior director of technical sales at ANSYS-Apache. “Having said that, RTL ‘signoff’ is not signoff in the traditional sense. It is not a guarantee of performance, power, or reliability specification. It is more of a structured quality check of the RTL that ensures that RTL is ready for the downstream flow.”
Ruby noted that while the big challenge is complexity, it is well understood that dealing with power consumption as early in the design flow and schedule as possible is a requirement. “But ensuring consistent accuracy of power consumption analysis at RTL compared to ‘real ‘signoff, such as post-layout power analysis, is no easy task. RTL signoff will get more challenging as we move forward, as additional physical effects, such as thermal, will need to be considered early in the design process.”
PPA becomes more difficult to assess
To a large extent, power has made the whole signoff equation far more complex than it used to be, especially at 28nm and below. It’s no longer an afterthought or something that can be fixed or even approximated, and getting it wrong can affect the basic premise for moving to the next process node.
“There are three challenges with signoff—leakage power, dynamic power and IR drop,” said Sudhakar Jilla, group product director for the Place & Route Division at Mentor Graphics. “At 28nm, and certainly at 20nm, leakage power is dominant. And at 16nm, because of the finFETs, capacitance on the pins is increa[sing and dynamic power is more important. In fact, you now need to address dynamic power at every step of the flow.”
That also means measurements have to be more accurate for power dissipation, the methodologies and tools need to change for dynamic power, and optimization needs to address leakage and area at the same time, Jilla said.
He’s not alone in that assessment. Ron Moore, vice president of marketing for ARM’s physical IP division, said that power analysis is required at every stage starting with early synthesis. “At 28nm and smaller, leakage on memory becomes a significant portion of the power budget. You have to analyze that plus dynamic power. And with finFETs, you have to lay down a power grid early in the floor plan. If you look back at 90nm, a lot of that was timing-driven design closure. In the future, it’s going to be power-driven.”
And Anirudh Devgan, corporate vice president of R&D for silicon signoff and verification at Cadence, said that signoff also has to be accurate and occur earlier in the flow. “To really do power signoff effectively you have to do the whole chip together and read all of the electrical information. Power used to be ad hoc analysis done later in the flow. But because you can’t have margin in the timing anymore at advanced nodes, it has to be done earlier.”
Not just checking the box
So what exactly has power signoff become? The answer appears to be something closer to a process than a single box check. If power, performance and area have always been the three variables for moving to the next node, power was always the last to be considered. It is now frequently the first to be considered at every level, with the final signoff something of a final check in that process.
“The check points are the same,” said Mark Baker, director of product marketing at Atrenta. “But because the design is larger and there is more IP, there is an increasingly daunting increase in analysis. You need to understand everything from the RTL level to an abstraction to manage clock domain crossing, design for test, constraints, and you have to make decisions early to have signoff checks for all of those. There is a lot more influence from context due to all the different modes of operation.”
The shift in this way of thinking began several years ago, according to Abhishek Ranjan, senior director of engineering at Calypto Design Systems. “Power signoff was a problem, but it was not a huge problem because you knew each IP and you could predict the final power. But with handheld devices like smartphones and tablets and the emphasis on IP re-use, you need new RTL with each application. We used to turn out a laptop every two years. Now there’s a new smartphone or tablet every six or nine months, so you have to think more about optimizing power early on and what kind of optimization really works.”