What to do when simulation isn’t fast enough.
As designs grow larger, the time spent verifying a project is growing longer as well. As a solution, some companies are trying to ‘shift-left’ their schedules. Verification via software simulators is not fast enough for large System-on-Chip (SoC) design projects, there-fore one option is to use an FPGA emulator to speed up the design process.
But what happens when a bug occurs? This document describes Aldec HES-DVMTM features that can help speed up debug and verification of the SoC, in order to achieve faster time-to-market.
To read more, click here.