D2S rolls out faster hardware for mask production and other apps.
Chip production is becoming more complex and expensive at each node.
As a result, chipmakers require a growing number of new manufacturing technologies to enable the next wave of devices at advanced nodes. In the fab, for example, the most obvious need is extreme ultraviolet (EUV) lithography. In addition, chipmakers also need a new class of atomic-level processing tools, metrology and inspection gear, among others.
There are also pressing needs in the photomask shop, including one technology–more computational horsepower. In fact, a growing number of applications in both the photomask shop and the fab require faster computations and for good reason—the data sets are becoming larger and more complex with each device generation.
Looking to address the issues in the mask shop and other applications, D2S has rolled out its fourth-generation computational design platform (CDP). Basically, the CDP is a specialized, GPU-based acceleration hardware platform that enables 400 teraflops of performance. A teraflop is a trillion floating point operations per second.
The CDP is actually based on a combination of both graphics processing units (GPUs) and microprocessors. More specifically, the system is powered by two of Nvidia’s K-80 GPUs and two of Intel’s Xeon E5-2630 v3 CPUs on each node.
In one mask data prep test, the CDP is said to be ten times faster than a CPU-only system. “Bringing the computation power of GPUs to simulating complex processes in semiconductor manufacturing opens up the potential for a wide variety of new applications,” said Aki Fujimura, chief executive of D2S.
D2S’ system is targeted for several applications. For example, it is being used for model-based mask data preparation (MB-MDP), where leading-edge photomasks are becoming increasingly complex. “You have more complexity of the shapes that you need to manipulate. You also have more shapes. And for each of those things, there is a demand to be more precise,” Fujimura said. “So if you have all of those things combined, it creates an increasingly difficult computational situation. All of that points to simulation-based processing.”
The system is also geared for CD-SEM metrology, mask writing and other applications. For example, it can be used for inline thermal-effect correction of e-beam mask writers as a means to reduce the write times.
“We need a fast data processing platform for complex features and also for multi-beam mask writers,” said Naoya Hayashi, research fellow at Dai Nippon Printing (DNP). “We need high-performance data processing capability to write a huge number of pixels in a second.”
On top of that, GPUs can also speed up EDA software tools. This is true for some but not all applications. In some cases, CPUs can do the job. “Massive parallel computation is still the path to contain run times, and we are continuing to invest and expand our technology in that direction with very good results using many-core CPUs,” said Juan Rey, senior director of engineering for Calibre at Mentor Graphics, in a recent interview.
In another example, Cadence recently acquired Rocketick Technologies, a developer of an x86-based acceleration solution. Using x86-based servers, Rocketick’s technology accelerates Cadence’s simulator in order to provide faster RTL, as well as gate-level and DFT simulations.
–Ann Steffora Mutschler contributed to this report.
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