SpyGlass Flow For Xilinx FPGA

As FPGAs become an attractive alternative to SoC-type designs, verification is becoming a major challenge.


As the cost of doing ASIC design skyrockets, FPGAs are becoming an attractive alternative for system-on-chip (SoC) types of design. Large numbers of increasingly complex designs are now done with FPGAs, making verification a major task. Besides the usual issues of width mismatch, connectivity or synthesis-simulation mismatch, there are also problems related to multiple asynchronous clock domain crossings (CDC) like meta-stability, data re-convergence, FIFO integrity, and more.

Given that a verification flow using SpyGlass for ASICs already exists for the problems highlighted above, this document describes the steps required to take an RTL design for XILINX FPGAs through SpyGlass to make it Lint and CDC clean.

A typical SpyGlass flow for an RTL design is as follows:


The figure highlights the various types of problems faced with different design components when the design is taken through SpyGlass. The subsequent sections will describe the problems and their solutions.

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