Stacking The Deck

Enabling 2.5D and 3D architecture and the supply chain.

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By Javier DeLaCruz
The pinnacle of system-on-chip has passed. There are several dynamics that are moving the industry away from the SoC philosophy that was so popular just a few short years ago. One of the significant factors is that the cost per gate for CMOS nodes below 28nm is rising for the first time in the history of our industry. Another critical factor is the emergence of through-silicon-via (TSV) technology as a viable package element. Other factors include memory density’s inability to keep up with processing demand and the limitations of copper interconnects for high-speed signal transmission.

With these industry changes, several companies are shifting their crosshairs to technology enablers such as 2.5D and 3D integration. A key element is flexibility. But with 2.5D and 3D architectures, there are new links in the semiconductor supply chain, including:

  1. Interposer manufacturers;
  2. Tile suppliers (a tile is a die that is designed for 2.5D and 3D assemblies);
  3. Third-party foundry services for partial wafer processing.

In addition, existing links in the chain can become more complex:

  1. The ability to mix technologies and nodes opens the door for additional foundries for different components in the same 2.5D or 3D assembly.
  2. OSAT (outsourced assembly and test) can perform a more complex role and contribute more to the value chain as items such as memory stacks, optics, and MEMS devices can be integrated within the package. This poses an inventory challenge, a yield ownership challenge and a procurement challenge because OSATs are generally not keen to directly source these high-cost components.
  3. Test challenges are very significant because components within 2.5D and 3D assemblies may not be completely testable until the assembly is complete, which results in a higher monetary risk for each failed component. Novel approaches to mitigating these test and yield issues are required.

The die design process is also much more complex, as different types of interfaces must be used between 2.5D and 3D tiles than would be otherwise needed. These interfaces are much lower power and higher density than conventional SerDes or DDR interfaces. There is little reason to use a SerDes or a higher-voltage interconnect to simply go from one die to another in the same package. The architecture of such devices is dramatically different as the die need to be designed with a different type of hierarchy in order to leverage different wafer nodes and technologies. There is an opportunity to dramatically drop the power of 2.5D and 3D devices if the architecture is planned correctly and the IP and tiles are available.

There has been a heavy focus on the increased complexity at the package level introduced by the 2.5D and 3D package structures and resulting cost impact. While this is somewhat true, it has to be weighed against the simplified system-level integration. Most printed circuit boards (PCBs) in networking, storage and computing applications are very high- layer-count PCBs. These usually are used to gate the memory interface between a processor and the memory it accesses. If a 2.5D or 3D device has the memory already integrated into the package, then the PCB no longer would need nearly as many layers. In addition, with the memory included in the package at a higher bandwidth and capacity and lower power, the package interconnect count is reduced considerably. The memory interfaces that once dominated the ball assignments would be available for other functions or assigned as power supplies.

The main interface remaining would be high-speed SerDes and eventually optical interconnects. Therefore, the area efficiency of 2.5D and 3D devices compared to traditional ASICs (including the area taken by the field of memory) would be vastly improved. Furthermore, the complexity of assembly on a given board (assuming similar functionality) also would be simpler. In our discussions with OEMs, none of them would actually keep the same functionality on a PCB. Instead, they would simply put more processing power on the same PCB, mainly due to the area savings of a 2.5D or 3D approach. They would still benefit from a lower PCB layer count.

As the market shifts towards 2.5D and 3D integration, IP suppliers have a potential role change as usage of their IP becomes similar to a standalone piece of physical silicon. Hence, these companies can leverage their expertise to sell standard product instead of just IP.

2.5D and 3D ICs: A New Landscape
With higher levels of co-design required for these devices, several links in the chain are not correctly prepared for this increased interaction. OSATs generally do not have the expertise in device architecture needed to effectively take advantage of the key benefits of this type of device. Alternatively, with the lack of industry standards in test interfaces, bump geometries, interposer types, interface patterns, etc., there are too many open variables to easily decide where to start planning. eSilicon’s MoZAIC™ program has developed interface patterns that work in a variety of interposer technologies and have activity in place to qualify these at multiple OSATs. This data—along with integrated architecture planning, a future library of existing tiles and a solution that can be reliably assembled—will enable customers to cover the new complexities introduced with 2.5D and 3D architectures and allow them to focus on truly leveraging the benefits of 2.5D and 3D with their new devices.

Factors Influencing the Transition to 2.5D and 3D ICs

—Javier DeLaCruz is senior director of engineering at eSilicon Corporation.