Time For A DDR Background Check

In this month’s blog we continue our discussion of power management, specifically looking at how architects can improve the energy efficiency of their SoC as it uses system memory. In March we teamed up with Micron, a global supplier of high performance, low power memory technologies, to present a tutorial at SNUG Silicon Valley (see proceedings) explaining the practical steps system desig... » read more

Advanced Analog And Mixed Signal Design Continues Pushing The Design Envelope

As PCB design has evolved into its present form with extremely complex boards housing high speed circuitry in very small areas, analog and mixed signal (AMS) and high speed analysis can address the latest design challenges. Analog/mixed signal design More and more products incorporate more than just digital circuitry. The vast majority of products now integrate digital and analog circuitr... » read more

Optimizing DDR Memory Subsystem Efficiency

The memory subsystem sits at the core of a System-on-Chip (SoC) platform and can make all the difference between a well-designed system meeting its performance requirements and a system that delivers poor performance, or even fails to operate correctly. State-of-the-art DDR memory controllers use advanced arbitration and scheduling policies to optimize DDR memory efficiency. At the same time, t... » read more

What’s Next For DRAM?

The DRAM business has always been challenging. Over the years, DRAM suppliers have experienced a number of boom and bust cycles in a competitive landscape. But now, the industry faces a cloudy, if not an uncertain, future. On one front, for example, [getkc id="93" kc_name="DRAM"] vendors face a downturn amid a capacity glut and falling product prices in 2016. But despite the business chal... » read more

Electronics Butterfly Effect

Everyone has heard of the butterfly effect where a small change in a non-linear system can result in large difference in an outcome. For the past 40 years, the electronics industry has approximated a linear system, fed primarily by Moore’s Law. The incremental changes available at each new process node have led us to make incremental changes and improvements in many aspects of the design, its... » read more

Memory Directions Uncertain

Semiconductor Engineering sat down with a panel of experts to find out what is happening in world of memories. Taking part in the discussion are [getperson id="11073" comment="Charlie Cheng"], chief executive officer at [getentity id="22135" e_name="Kilopass Technology"]; Navraj Nandra, senior director of marketing for Analog/Mixed signal IP, embedded memories and logic libraries at [getentity ... » read more

Advances In Power Management For Physical IP In 28nm And FinFET Process Nodes

Engineering techniques to reduce power consumption by lowering the supply voltage and slowing the clock speed have reached practical limits of the semiconductor technologies. Newer solutions, which not only reduce power but also actively manage the power during the course of the SoC (system on chip) activity, are emerging. This article describes these innovations from the foundation intellectua... » read more

DDR White Paper

DDR DRAM memory controllers have many competing demands on them. A good memory controller must improve the bandwidth of the memory interface while respecting the latency demands of the CPU, graphics, and real-time DRAM in the system while maintaining compliance with memory bus and on-chip bus standards. The read reorder buffer (RRB) is a silicon-proven architectural enhancement available in... » read more

Case Study: Microsemi Memory Interface

Microsemi qualified a structured approach to mixed-signal SoC verification using Questa ADMS, systematic pre-planning, and the OVM. To view this white paper, click here. » read more