More Nodes, New Problems


The rollout of leading-edge process nodes is accelerating rather than slowing down, defying predictions that device scaling would begin to subside due to rising costs and the increased difficulty of developing chips at those nodes. Costs are indeed rising. So are the number of design rules, which reflect skyrocketing complexity stemming from multiple patterning, more devices on a chip, and m... » read more

New Patterning Options Emerging


Several fab tool vendors are rolling out the next wave of self-aligned patterning technologies amid the shift toward new devices at 10/7nm and beyond. Applied Materials, Lam Research and TEL are developing self-aligned technologies based on a variety of new approaches. The latest approach involves self-aligned patterning techniques with multi-color material schemes, which are designed for us... » read more

Nodes Vs. Nodelets


Foundries are flooding the market with new nodes and different process options at existing nodes, spreading confusion and creating a variety of challenges for chipmakers. There are full-node processes, such as 10nm and 7nm, with 5nm and 3nm in R&D. But there also is an increasing number of half-nodes or "node-lets" being introduced, including 12nm, 11nm, 8nm, 6nm and 4nm. Node-lets ar... » read more

The Next 5 Years Of Chip Technology


Semiconductor Engineering sat down to discuss the future of scaling, the impact of variation, and the introduction of new materials and technologies, with Rick Gottscho, CTO of [getentity id="22820" comment="Lam Research"]; Mark Dougherty, vice president of advanced module engineering at [getentity id="22819" comment="GlobalFoundries"]; David Shortt, technical fellow at [getentity id="22876" co... » read more

Fan-Outs vs. TSVs


Two years ago, at the annual IMAPS conference on 2.5D and 3D chip packaging, the presentations were dominated by talk of fan-out wafer-level packaging. There was almost no talk of through-silicon vias, which previously had been heralded as vital to 2.5D and 3DIC packaging. Fast forward to this month's 3D Architectures for Heterogeneous Integration and Packaging conference in Burlingame, Cali... » read more

What’s After 7nm?


The rollout of 10/7nm was a long time coming, and for good reason. It's hard stuff, and chipmakers have to be ready to take a giant step forward with new processes, tools, and to deal with a slew of physical effects that no longer can be handled by just guard-banding a design. The big question is what's next, when it will happen, and how much it will cost. Preparing for the next process node... » read more

The Secret Life Of Accelerators


Accelerator chips increasingly are providing the performance boost that device scaling once provided, changing basic assumptions about how data moves within an electronic system and where it should be processed. To the outside world, little appears to have changed. But beneath the glossy exterior, and almost always hidden from view, accelerator chips are becoming an integral part of most des... » read more

Shrink Or Package?


Advanced packaging is rapidly becoming a mainstream option for chipmakers as the cost of integrating heterogeneous components on a single die continues to rise. Despite several years of buzz around this shift, the reality is that it has taken more than a half-century to materialize. Advanced [getkc id="27" kc_name="packaging"] began with IBM flip chips in the 1960s, and it got another boost ... » read more

Playing With Chip Volumes


The overall market for semiconductors continues to grow, but the number of applications that will generate enormous volumes continues to shrink. In theory, this is good for the overall semiconductor industry, but it raises important questions about where R&D dollars will go in the future. The fundamental problem is that the semiconductor business is a volume business for one or two markets. ... » read more

The Return Of Time Sharing


As early as the 1960s, it wasn't uncommon to hear that transistors would be free. Those were pretty bold statements at the time, considering most computers in those days cost $1 million, required special rooms, and budding computer scientists usually had to sign up to use mainframe computers for one-hour time slots—often in the middle of the night or on weekends. Still, those predictions ... » read more

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