Multi-Patterning Issues At 7nm, 5nm


Continuing to rely on 193nm immersion lithography with multiple patterning is becoming much more difficult at 7nm and 5nm. With the help of various resolution enhancement techniques, optical lithography using a deep ultraviolet excimer laser has been the workhorse patterning technology in the fab since the early 1980s. It is so closely tied with the continuation of [getkc id="74" comment="Mo... » read more

A Novel Approach To Dummy Fill For Analog Designs Using Calibre SmartFill


With small geometry silicon processes, additional nonfunctional geometric structures are required to maintain layer planarity during the chemical/mechanical polishing (CMP) phase of processing. The automated layout flows to generate such geometries tend to be designed primarily for large system on chip (SOC) digital designs. When applied to mixed-signal layouts, these flows have been seen to ha... » read more

Betting On Power And Deep Learning


Jim Hogan, managing partner of Vista Ventures, sat down with Semiconductor Engineering to talk about what investments deliver the biggest returns, how quickly, and why there are so few investors in some big growth areas. What follows are excerpts of that conversation. SE: What are you investing in these days and why? Hogan: I have about 15 active deals right now. I generally invest in thi... » read more

The Pitfalls Of Auto-Stitching In Double-Patterning


Ever since the first double-pattern (DP) odd-cycle error ring was produced on a layout, designers have longed for a magic solution to solve it. Traditionally, the first approach to fixing an odd-cycle error was to move a polygon or a polygon edge to increase spacing to an adjoining polygon in the cycle. Alternatively, you could remove a polygon altogether, or split it into two pieces. All of th... » read more

Design Process Technology Co-Optimization For Manufacturability


Yield and cost have always been critical factors for both manufacturers and designers of semiconductor products. Meeting yield and product cost targets is a continuous challenge, due to new device structures and increasingly complex process innovations introduced to achieve improved product performance at each new technology node. Design for manufacturability (DFM) and design process technology... » read more

LVS Boxing Helps Designers Knock Out Designs Quickly


Keeping up with the constant demand for better, faster design flow performance while preserving the original layout hierarchy of a design can be very challenging during design verification. Designers must constantly manage tradeoffs between performance, database size, and accuracy. In the early design cycle, using the LVS boxing capabilities of Calibre nmLVS to replace incomplete or missing blo... » read more

Pattern Matching In Test And Yield Analysis


By Jonathan Muirhead and Geir Eide It’s no secret that a successful yield ramp directly impacts integrated circuit (IC) product cost and time-to-market. Tools and techniques that help companies ramp to volume faster, while also reducing process and design variability, can be the difference between profit and loss in a competitive market. And while pattern matching technology has been aroun... » read more

A Pattern Of Success: Calibre Pattern Matching


Calibre Pattern Matching allows you to define specific geometric configurations as visual patterns, directly from a design layout. With this visual representation, Calibre Pattern Matching opens up a whole new way to define design rules for both established and advanced nodes, and enables a wide range of innovative applications across design, verification, and test. This white paper introduces ... » read more

LVS Boxing Helps Designers Knock Out Designs Quickly


Keeping up with the constant demand for better, faster design flow performance while preserving the original layout hierarchy of a design can be very challenging during design verification. Designers must constantly manage tradeoffs between performance, database size, and accuracy. In the early design cycle, using the LVS boxing capabilities of Calibre nmLVS to replace incomplete or missing blo... » read more

Tech Talk: Double-Triple Patterning


Mentor Graphics' David Abercrombie shows the differences and challenges in double patterning versus triple patterning. [youtube vid= e0wZmjBbEf0] » read more

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