tag: DRC

Earlier SoC Design Exploration And Verification Gets Better Designs To Tapeout Faster
By Nermeen Hossam - 25 Aug, 2022 - Comments: 0

By Nermeen Hossam and John Ferguson Between the complexity of advanced node design verification and the competition to be first to the market, system-on-chip (SoC) designers no longer have the luxury of waiting until each sub-block of a chip is DRC-clean to start their chip assembly and verification. Today’s SoC designers typically start chip integration in parallel with block development.... » read more

IC Reliability Burden Shifts Left
By Ann Mutschler - 23 Jun, 2022 - Comments: 0

Chip reliability is coming under much tighter scrutiny as IC-driven systems take on increasingly critical and complex roles. So whether it's a stray alpha particle that flips a memory bit, or some long-dormant software bugs or latent hardware defects that suddenly cause problems, it's now up to the chip industry to prevent these problems in the first place, and solve them when they do arise. ... » read more

Reliable DRC Voltage Text Annotation Means Faster And More Accurate DRC Verification
By Abdellah Bakhali - 14 Apr, 2022 - Comments: 0

As the potential for complex interactions between voltage domains grows significantly with the increase in design density at each new process node, the complexity of spacing checks in design rule checking (DRC) also increases. To minimize these types of risk, many simple spacing checks have evolved to become voltage-aware DRC (VA-DRC) checks that incorporate voltage values to determine the requ... » read more

Automated DRC Voltage Annotation Provides Faster And More Accurate Verification For Voltage-Aware Spacing Rules
By Siemens EDA - 13 Apr, 2022 - Comments: 0

Accurate and repeatable reliability verification is now essential for both advanced node designs and the increasingly complex products being produced at established nodes. To ensure compliance with all process, reliability, and power management requirements, voltage-aware DRC applies variable spacing requirements, based on either the absolute voltage or delta voltage values, to accurately evalu... » read more

Challenges With Stacking Memory On Logic
By Ed Sperling - 22 Dec, 2021 - Comments: 1

Experts at the Table: Semiconductor Engineering sat down to discuss the changes in design tools and methodologies needed for 3D-ICs, with Sooyong Kim, director and product specialist for 3D-IC at Ansys; Kenneth Larsen, product marketing director at Synopsys; Tony Mastroianni, advanced packaging solutions director at Siemens EDA; and Vinay Patwardhan, product management group director at Cadence... » read more

Batch Filters: A Better, Faster Way To Filter Large DRC Results Databases
By Siemens EDA - 22 Nov, 2021 - Comments: 0

Reviewing massive DRC results databases (RDBs) can be a time-consuming stage in traditional debug flows, due primarily to the loading, filtering, and display times associated with these large datasets. Finding the most effective approach to filtering results data is important to optimize both results debug time and resource usage. While smaller databases that load quickly in GUI applications ca... » read more

Microchip Sees Significant Productivity Gains In Mature-Node Custom IC Design With In-Design Signoff DRC
By Siemens EDA - 27 Oct, 2021 - Comments: 0

Microsemi pioneered the design of innovative chips that are used for multiple purposes across a variety of industries, using both mature and advanced process nodes. In mature node custom design implementation, layout designers still spend a significant amount of their valuable time fixing DRC errors—time that could be more beneficially spent ensuring their designs meet their PPA goals. By rep... » read more

In-Design Signoff DRC For Productivity Improvement
By Srinivas Velivala - 26 Aug, 2021 - Comments: 0

Microsemi, a wholly-owned subsidiary of Microchip Technology, produces a portfolio of semiconductor and system solutions for communications, defense and security, aerospace, and industrial markets. In addition to high-performance and radiation-hardened analog/mixed-signal integrated circuits, FPGAs, SoCs and ASICs, they also design power management products, timing and synchronization devices, ... » read more

Optimize Physical Verification Cost Of Ownership
By Manoz Palaparthi - 29 Jul, 2021 - Comments: 0

As semiconductor designs continue to grow in size and complexity, they put increasing pressure on every stage of the design process. Physical verification, often on the critical path to tape-out, is especially affected. Design rule checking (DRC), layout versus schematic (LVS), and other physical verification runs take longer as chip size increases. In addition, finer geometries introduce new c... » read more

Tape Out On Time With Demand Signoff DRC In P&R
By Siemens EDA - 28 Jul, 2021 - Comments: 0

Physical characteristics of devices have become progressively more complex even as design companies pack more devices on each die. Combining these characteristics with ever more demanding chip power, performance, and area (PPA) goals not only result in increased resource utilization but also challenge existing tools/flows/techniques. Adding on-demand signoff-quality DRC verification inside P&R ... » read more

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