tag: embedded deterministic test

The Era Of Packetized Scan Test Has Arrived
By Geir Eide - 07 Sep, 2021 - Comments: 0

For decades, process and design scaling has triggered the adoption of transformative test solutions. About twenty years ago, when at-speed test became a de-facto requirement, on-chip compression became the norm to address test data time and volume. Over the last decade, hierarchical DFT enabled DFT engineers to apply a divide and conquer on large design, improving both implementation effort and... » read more

New Memories Add New Faults
By Bryon Moyer - 07 Sep, 2021 - Comments: 1

New non-volatile memories (NVM) bring new opportunities for changing how we use memory in systems-on-chip (SoCs), but they also add new challenges for making sure they will work as expected. These new memory types – primarily MRAM and ReRAM – rely on unique physical phenomena for storing data. That means that new test sequences and fault models may be needed before they can be released t... » read more

Planning Ahead For In-System Test Of Automotive ICs
By Jeff Mayer - 14 Jan, 2020 - Comments: 0

Automobiles are increasingly more like electronic devices than mechanical platforms. As a share of the total cost of a car, electronics components have grown from about 5% in 1970 to 35% in 2010. Electronics are projected to account for 50% by 2030 (Deloitte, 2019). Some of the electronics are for passive operations, like display or In-Vehicle Infotainment (IVI) systems, but a growing proportio... » read more

Squeezing Out More Test Compression
By Jeff Mayer - 10 Dec, 2019 - Comments: 0

The trend in semiconductors leads to more IC test data volume, longer test times, and higher test costs. Embedded deterministic test (EDT) has continued to deliver more compression, which has been quite effective at containing test costs. For many designs, standard test compressions is enough, but ICs for use in automotive and medical devices require a higher manufacturing test quality, which t... » read more

EDT Test Points
By Mentor, a Siemens Business - 22 Jan, 2015 - Comments: 0

Embedded test compression was commercially introduced over a decade ago and has scaled to well beyond the 100X range envisioned when it was first introduced. However, growing gate counts enabled by new technology nodes as well as new fault models targeting defects within standard cells are driving the need for even greater compression levels. This paper describes an exciting new technology, cal... » read more

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