Measuring Verification Productivity

By Ann Steffora Mutschler In this era of mammoth SoCs that require the utmost in verification complexity, it’s not enough to have a methodology. Design and verification teams also need to measure their productivity to constantly stay ahead of the curve. The more sophisticated customers are measuring a lot of things, explained Steve Bailey, marketing director at Mentor Graphics, “and for... » read more

Transitioning States

By Ann Steffora Mutschler While the concept of finite state machines is mature, understanding their role in design, the transitions between them and how to verify them are fundamental to managing power in today’s large SoCs. In essence, a finite state machine is a set of inputs and outputs and gate bits that describes the operation of the system. “Transitions happen from one state to... » read more

Techniques For FSM Design And Verification

Large system-on-chip (SoC) designs contain many finite state machines (FSMs) that interact with data paths, memories, and other components. Although FSMs are critical building blocks many designers lack an understanding of their role and impact on design quality and validation effort. FSMs are a source of functional bugs in SoCs. They can cause poor timing, power, and performance. Although v... » read more