Synopsys Buys Gold Standard Simulations

[getentity id="22035" e_name="Synopsys"] has made another quiet acquisition, this time in the TCAD space. [getentity id="22272" comment="Gold Standard Simulations (GSS)"] offers a suite of solutions for design technology co-optimization (DTCO), PDK development and exploration and screening of future technology options. Their tool chain integrates predictive Monte Carlo and statistical TCAD s... » read more

Transistor-Level Verification Returns

A few decades ago, all designers did transistor-level verification, but they were quite happy to say goodbye to it when standard cells provided isolation at the gate-level and libraries provided all of the detailed information required, such as timing. A few dedicated people continued to use the technology to provide those models and libraries and the most aggressive designs that wanted to stri... » read more

Why DSA Is Cost Effective For 7nm And Below

The upcoming 7nm process node presents tough challenges both for printability and cost. At 7nm and below, multi-patterning is required, which makes the manufacturing process more expensive by requiring more masks. To control costs, any alternative technology that provides equivalent yields with fewer patterning steps should be explored. One promising option is to use directed self-assembly (... » read more

Moore Memory Problems

The six-transistor static memory cell (SRAM) has been the mainstay of on-chip memory for several decades and has stood the test of time. Today, many advanced SoCs have 50% of the chip area covered with these memories and so they are critical to continued scaling. “The SRAM being used in modern systems is similar to the SRAM they were using in the 1970s and 1980s,” says Duncan Bremner, ch... » read more

Blog Review: May 21

Mentor’s Colin Walls offers up some new insights into C++ exception handling, thanks to some input from colleague Jonathan Roelofs. This one involves minimizing overhead and reducing runtime penalties. Synopsys’ Mick Posner is back in the saddle again—literally. This is about as green as it gets. Cadence’s Arthur Marris reports back on the IEEE 802.3 Ethernet standards meeting, in... » read more

Leveraging The Past

By Ann Steffora Mutschler It’s easy to forget that not every design today is targeted at 20nm, given the amount of focus put on the bleeding edge of technology. But in fact a large number of designs utilize the stability and reliability of older manufacturing nodes, as well as lower mask costs, by incorporating new design and verification techniques, with 2.5D designs being a prime example. ... » read more