The Future of UVM


It’s time for a frank discussion on the future of [gettech id="31055" comment="UVM"]. Given how UVM usage has grown and the number of teams that rely on it, I think this conversation has been a long time coming. Is continuing to use UVM the right thing to do? Do we have hard evidence that supports our continued usage of UVM? Do we actually benefit from it or do we just think we benefit? ... » read more

Optimizing Testbench Acceleration Performance


Part 3 in a series of papers that demystify the performance of SystemVerilog and UVM testbenches when using an emulator for the purpose of hardware-assisted testbench acceleration. In these three papers, architectural and modeling requirements are described, followed by a recommended systematic approach for maximizing overall testbench acceleration speed-up and achieving your ultimate performan... » read more

Turning Verification Inside Out


A new motivation for rebalancing came to me during a conversation I had a couple weeks ago at the Agile Alliance Technical Conference. I had the chance to compare my day-to-day responsibilities with those of Lisa Crispin. Lisa is a software test expert that is very well regarded within the [getkc id="182" comment="Agile Development"] community. Think of her as a Harry Foster/Janick Bergeron typ... » read more

Seeing Debug for What It Is


Debug is problem solving. For many hardware developers, debug is a purpose. Finding a bug is a victory! Heck, debug can be flat out heroic. I’m sure we can all think back to colleagues that put in a few 80 hour, coffee fueled weeks, with managers peering over both shoulders, to fix an insidious string of bugs that threatened to further demolish a broken schedule and sabotage tape-out. W... » read more

Still Time to Blow Up UVM


Blowing up UVM is something I ran on my own blog a few years ago. Considering not much has changed with respect to UVM – that it continues to dominate verification circles – I figured it’s a discussion worth re-starting. In my mind, it’s not too late to take a few steps forward by blowing up UVM. A little history… the idea to blow up UVM was motivated by a slide snapshot posted to ... » read more

Power Estimation: Early Warning System Or False Alarm?


Semiconductor Engineering sat down with a large panel of experts to discuss the state of power estimation and to find out if the current levels of accuracy are sufficient to being able to make informed decisions. Panelists included: Leah Schuth, director of technical marketing in the physical design group at [getentity id="22186" comment="ARM"]; Vic Kulkarni, senior vice president and general m... » read more

DAC 2015: Day 3


The schedule for today revolves around eating and it is perfectly balanced between the big three. The morning starts with breakfast for the Cadence panel titled "Crossing the Great Divide: How to Safely Navigate the move from 28nm to 16FF+." The panel was moderated by Brian Fuller and panelists included Jayanta Lahiri from ARM, Afshin Montaz from Broadcom, Scott McCormack from Freescale, Yan... » read more

Yikes! Why Is My SystemVerilog Testbench So Slooooow?


It turns out that [gettech id="31023" comment="SystemVerilog"] != [gettech id="31017" comment="verilog"]. OK, we all figured that out a few years ago as we started to build verification environments using [gettech id="31026" comment="IEEE 1800"] SystemVerilog. While it did add design features like new ways to interface code, it also had verification features like classes, dynamic data types, ... » read more