Tech Talk: Automotive Design


NetSpeed Systems CEO Sundari Mitra talks about how to speed up the design of automotive chips. https://youtu.be/cus4fStDa5c » read more

Tech Talk: eFPGA Density


Chen Wang, senior vice president of engineering at Flex Logix, talks about how to improve density in embedded FPGAs. https://youtu.be/Rk0oqzWQr8I » read more

Why Auto Designs Take So Long


Designing chips for the automotive market is adding significant overhead, particularly for chips with stringent safety requirements. On the verification side it could result in an additional 6 to 12 months of work. On the design side, developing the same processor in the mobile market would take 6 fewer man months. And when it comes to complex electronic control units (ECUs) or [getkc id="81... » read more

Find The Best IP For You


It can be quite challenging and time consuming to find the right semiconductor IP for your project. You’ve got to find IP that does not consume too much power, meets your performance target, has the lowest leakage when your product goes on standby, and last but not least, IP that occupies the least amount of expensive real estate on your chip. How can you accomplish such a task without having... » read more

Accelerating Monte Carlo Analysis At Advanced Nodes


Advanced-node designs have much larger variation, making it much more difficult to achieve high yields at these processes. But can you really afford to run thousands or even millions of statistical simulations to predict how well your design will meet its specs? Or overdesign to accommodate manufacturing variations? In this paper, we will introduce a fast Monte Carlo analysis technique that del... » read more

Executive Insight: Sehat Sutardja


Sehat Sutardja, chairman and CEO of Marvell, sat down with Semiconductor Engineering to talk about new approaches for design and memory and why costs and time to market are forcing changes in Moore's Law. What follows are excerpts of that conversation. SE: What was behind your move into modular packaging? Sutardja: The cost of building chips is getting out of hand. As we make things more ... » read more

What Goes Wrong With IP


Semiconductor Engineering sat down to talk about the future of IP with Rob Aitken, R&D fellow at [getentity id="22186" comment="ARM"]; Mike Gianfagna, vice president of marketing at [getentity id="22242" e_name="eSilicon"]; Judd Heape, vice president of product applications at Apical; and Bernard Murphy, an independent industry consultant. What follows are excerpts of that discussion, which... » read more

Tech Talk: 14nm And Stacked Die


Aashish Malhotra, marketing director for the ASIC Business Unit at GlobalFoundries, talks about 14nm process technology, the IP ecosystem, and why that technology node will be used as a platform for 2.5D and 3D stacked die across a wide range of markets including the Internet of Everything. [youtube vid=ukTRuedB7ZU] » read more

Smart Early ASIC Design Prototyping And Analysis


The Power Delivery Network (PDN) is the backbone of ASIC design. It is used to supply clean power to active circuits in the IC. Voltage drop on the power rails can result in degraded performance, making delivery of noise free supply to all design elements including die, package and PCB, a challenging task. With increasing competition in the market, delivering chips on time with 'first silico... » read more

Evaluation Platforms Key To Complex IP Integration


Just because a chip is complex to build doesn’t mean it has to take a long time. Runaway complexity in SoC and ASIC design is forcing chip companies to consider different methodologies and approaches that could actually simplify and speed up the whole process. The first step in this process was commercial IP, and its growing popularity attests to the fact that chipmakers are looking for... » read more

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