Trimming Waste In Chips


Extra circuitry costs money, reduces performance and increases power consumption. But how much can really be trimmed? When people are asked that question they either get defensive or they see it as an opportunity to show the advantages of their architecture, design process or IP. The same holds true for IP suppliers. Others point out that the whole concept of waste is somewhat strange, becau... » read more

Noise Abatement


[getkc id="285" kc_name="Noise"] is a fact of life. Almost everything we do creates noise as a by-product and quite often what is a signal to one party is noise to another. Noise cannot be eliminated. It must be managed. But is noise becoming a larger issue in chips as the technology nodes get smaller and packaging becomes more complex? For some, the answer is a very strong yes, while for ot... » read more

Is Design Innovation Slowing?


Paul Teich, principal analyst for Tirias Research, gave a provocative talk at the recent DAC conference entitled, "Is Integration Leaving Less Room for Design Innovation?" The answer isn't as simple as the question might suggest. "Integration used to be a driver for increasing the functionality of silicon," Teich said. "Increasingly, it will be used to incorporate more features of an entire ... » read more

IP Challenges Ahead


The revenue from semiconductor [getkc id="43" kc_name="IP"] has risen steadily to become the largest segment of the EDA industry. Industry forecasts expect it to keep growing at a CAGR of more than 10% for the next decade. Part one of this article examined the possibility those forecasts are wrong and that large semiconductor companies are likely to start bringing IP development back in hous... » read more

Dealing With System-Level Power


Analyzing and managing power at the system level is becoming more difficult and more important—and slow to catch on. There are several reasons for this. First, design automation tools have lagged behind an understanding of what needs to be done. Second, modeling languages and standards are still in flux, and what exists today is considered inadequate. And third, while system-level power ha... » read more

The Week In Review: Manufacturing


Market research SEMI has released its mid-year forecast at Semicon West. SEMI reported that worldwide sales of new semiconductor manufacturing equipment are projected to increase by 19.8% to a total of $49.4 billion in 2017, marking the first time that the semiconductor equipment market has exceeded the market high of $47.7 billion set in 2000. In 2018, 7.7% growth is expected, resulting in an... » read more

IoT Myth Busting


The [getkc id="76" comment="Internet of Things"] (IoT) means many things to a large number of people, but one thing is clear—every discussion involving the IoT invariably includes some rather dramatic growth predictions for how many connected devices will be sold and who will be the primary beneficiaries. While that data helps spice up speeches, and typically gets people to read and quote ... » read more

Is The IP Industry Healthy?


The semiconductor industry has been through many changes, each designed to reduce the total cost associated with the design and manufacture of chips. Twenty years ago, most companies had their own fabs and designed all of the circuitry on each chip. Today, only a handful of companies still own a fab and outsourcing design, in the form of intellectual property ([getkc id="43" kc_name="IP"]), has... » read more

The Week In Review: Design


Tools Mentor added new tools to its high-level synthesis portfolio. The DesignChecks tool helps find bugs during coding with a static mode that performs very fast linting-like checks of the code and a formal mode that uses a formal engine for a more exhaustive proof of issues. The synthesis-aware Coverage tool measures code coverage for C++ signoff and fast closure of synthesized RTL. It sup... » read more

RISC-V Pros And Cons


Simpler, faster, lower-power hardware with a free, open, simple instruction set architecture? While it sounds too good to be true, efforts are underway to do just that with RISC-V, the instruction-set architecture (ISA) developed by UC Berkeley engineers and now administered by a foundation. It has been known for some time that with [getkc id="74" comment="Moore's Law"] not offering the same... » read more

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