Faster Time To Root Cause With Diagnosis-Driven Yield Analysis

ICs developed at advanced technology nodes of 65 nm and below exhibit an increased sensitivity to small manufacturing variations. New design-specific and feature-sensitive failure mechanisms are on the rise. Complex variability issues that involve interactions between process and layout features can mask systematic yield issues. Without improved yield analysis methods, time-to-volume is delayed... » read more

Yield Ramp Challenges Increase

As semiconductor manufacturing moves down to smaller process nodes, there’s no doubt that it is increasingly difficult to ramp both test and manufacturing yields. One reason for this is simply scale. Smaller nodes translate into more steps and greater complexity in the manufacturing process, with attendant process variations. “Smaller process nodes increase the amount of embedded mem... » read more

Root Cause Deconvolution

Scan logic diagnosis turns failing test cycles into valuable data and is an established method for digital semiconductor defect localization. The advent of layout-aware scan diagnosis represented a dramatic advance in diagnosis technology because it reduces suspect area by up to 85% and identifies physical net segments rather than entire logic nets [1-3]. The defect classifications provided by ... » read more