Finally, Realizing The Full Benefits Of Parallel Site-To-Site (S2S) Testing


A very common and well-known practice by manufacturers during the IC test process is to test as many of the device die or packaged parts as possible in parallel (i.e. sites) during wafer sort and final test in order to increase test time efficiency and lower overall test costs. The constraints that typically restrict how many test sites can be used at any given time are the design I/O and capac... » read more

Understanding How Small Variations In Photoresist Shape Significantly Impact Multi-Patterning Yield


Multi-patterning schemes such as Self-Aligned Double Patterning (SADP) and Self-Aligned Quadruple Patterning (SAQP) have been used to successfully increase semiconductor device density, circumventing prior physical limits in pattern density. However, the number of processing steps needed in these patterning schemes can make it difficult to directly translate a lithographic mask pattern to a fin... » read more

Patterning Problems Pile Up


Chipmakers are ramping up 16nm/14nm finFET processes, with 10nm and 7nm now moving into early production. But at 10nm and beyond, chipmakers are running into a new set of problems. While shrinking feature sizes of a device down to 10nm, 7nm, 5nm and perhaps beyond is possible using current and future fab equipment, there doesn't seem to be a simple way to solve the edge placement error (EPE)... » read more

MEMS: Improving Cost And Yield


MEMS devices inspire awe on the design side. On the test and manufacturing side, they evoke a different kind of reaction. These are, after all, the intersection of mechanical and electrical engineering—a joining of two miniature worlds that are the basis of some of the most complex technology on the planet. But getting these devices to yield sufficiently, understanding what does or does no... » read more

The Final Days…Getting To Sign-Off Faster With Calibre


With deadlines looming, the design flow between router output and final tape release can be stressful and frustrating. By combining a focused set of commands into macros, the Calibre YieldEnhancer tool enables designers to create customized, automated flows for engineering change order (ECO) filling, passive device insertion, custom fill to increase densities, jog removal, and via enhancements.... » read more

Transferring Skills Getting Harder


Rising complexity in developing chips at advanced nodes, and an almost perpetual barrage of new engineering challenges at each new node, are making it more difficult for everyone involved to maintain consistent skill levels across a growing number of interrelated technologies. The result is that engineers are being forced to specialize, but when they work with other engineers with different ... » read more

Expose Transistor-Level Yield Limiters With Cell-Aware Diagnosis


Cell-aware diagnosis is a new and effective method to perform transistor-level diagnosis to identify defects inside standard cells. It leverages fault models derived from analog simulation and uses a fail data collection and diagnosis flow identical to that of traditional diagnosis. Cell-aware diagnosis in Tessent Diagnosis is the result of over 10 years of research in cell-aware test and was d... » read more

BEOL Issues At 10nm And 7nm


Semiconductor Engineering sat down to discuss problems with the back end of line at leading-edge nodes with Craig Child, senior manager and deputy director for [getentity id="22819" e_name="GlobalFoundries'"] advanced technology development integration unit; Paul Besser, senior technology director at [getentity id="22820" comment="Lam Research"]; David Fried, CTO at [getentity id="22210" e_name... » read more

Stacked Die Changes


Semiconductor Engineering sat down to discuss advanced packaging with David Pan, associate professor in the department of electrical and computer engineering at the University of Texas; Max Min, senior technical manager at [getentity id="22865" e_name="Samsung"]; John Hunt, senior director of engineering at ASE; and Sitaram Arkalgud, vice president of 3D portfolio and technologies at Invensas. ... » read more

Faster Time To Yield


Michael Jamiolkowski, president and CEO of Coventor, sat down with Semiconductor Engineering to talk about ways improve yield ramp and optimize designs. What follows are excerpts of that conversation. SE: Why does it take so long to get a chip all the way through to manufacturing? Jamiolkowski: There are three parts to that. There is a research side. You want to be able to explore new th... » read more

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