The Next 5 Years Of Chip Technology


Semiconductor Engineering sat down to discuss the future of scaling, the impact of variation, and the introduction of new materials and technologies, with Rick Gottscho, CTO of Lam Research; Mark Dougherty, vice president of advanced module engineering at GlobalFoundries; David Shortt, technical fellow at KLA-Tencor; Gary Zhang, vice president of computational litho products at ASML; and Shay... » read more

7/5nm Timing Closure Intensifies


Timing closure issues are increasing in magnitude at 7/5nm, and ones that were often considered minor in the past no longer can be ignored. Timing closure is an essential part of any chip design. The process ensures that all combinatorial paths through a design meet the necessary timing so that it can run reliably at a specified clock rate. Timing closure hasn't changed significantly over th... » read more

Pattern-Based Analytics To Estimate And Track Yield Risk Of Designs Down To 7nm


Topological pattern-based methods for analyzing IC physical design complexity and scoring resulting patterns to identify risky patterns have emerged as powerful tools for identifying important trends and comparing different designs. In this paper, previous work is extended to include analysis of layouts designed for the 7nm technology generation. A comparison of pattern complexity trends with r... » read more

E-beam Inspection Makes Inroads


E-beam inspection is gaining traction in critical areas in fab production as it is becoming more difficult to find tiny defects with traditional methods at advanced nodes. Applied Materials, ASML/HMI and others are developing new e-beam inspection tools and/or techniques to solve some of the more difficult defect issues in the fab. [gettech id="31057" t_name="E-beam"] inspection is one of tw... » read more

Methodology For Analyzing And Quantifying Design Style Changes And Complexity Using Topological Patterns


In order to maximize yield, IC design companies spend a lot of effort to analyze what types of design styles are needed and used in their layouts (standard cells, macros, routing layers, and so forth). This paper introduces a novel methodology for full chip high performance topological pattern analysis and the applications of this methodology towards analyzing design styles in order to quanti... » read more

How To Sleep Easier If You Test Auto ICs For A Living


Last month, I looked at the product definition process of automotive ICs, using the $7 billion microcontroller market as an illustration of design exploration to optimize performance, features, die size and product cost. Now I’d like to look at the back end of the process — the final IC testing that’s still critical no matter how sound the upfront work in defining a featuring set and aptl... » read more

Improving Yield, Reliability With Data


Big data techniques for sorting through massive amounts of data to identify aberrations are beginning to find a home in semiconductor manufacturing, fueled by new requirements in safety-critical markets such as automotive as well as the rising price of packaged chips in smartphones. Outlier detection—the process of finding data points outside the normal distribution—isn't a new idea. It ... » read more

Filtering Out Fab Problems


Bertrand Loy, president and CEO of Entegris, sat down to discuss the semiconductor industry, process challenges and filter technology with Semiconductor Engineering. What follows are excerpts of that conversation. SE: What is the outlook for the IC industry? Loy: A lot of positive things are happening. Eighty percent of what we do are consumables, which would be chemistries and filters. ... » read more

A More Efficient Way To Calculate Device Specs Of Thousands Of Tests For Improved Quality And Yield


Today’s devices are required to pass thousands of parametric tests prior to being shipped to customers. A key challenge test engineers face, in addition to optimizing the number of tests they run on the device, is how to quickly and accurately define the true specification limits that should be used to determine if the device is “good”. Device specification limits that are too wide may... » read more

Finally, Realizing The Full Benefits Of Parallel Site-To-Site (S2S) Testing


A very common and well-known practice by manufacturers during the IC test process is to test as many of the device die or packaged parts as possible in parallel (i.e. sites) during wafer sort and final test in order to increase test time efficiency and lower overall test costs. The constraints that typically restrict how many test sites can be used at any given time are the design I/O and capac... » read more

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