There is nothing lean about 14nm designs.
Back in January, my article on dark silicon referenced work done by Michael Taylor and his research group at UC San Diego. I wasn’t able to arrange an interview with Dr. Taylor in time for that article, but we did have an extended conversation earlier this week. He pointed out that, while further decreases in threshold voltage are constrained by device leakage, the energy consumed by a circuit is actually given by CV², the capacitance times the voltage squared. Capacitance continues to go down, and energy reductions have, in his view, become the economic driving force for continued scaling.
The resulting need to manage and exploit dark silicon presents major challenges for designers. Heterogenous hardware introduces new complexity, while the use of design “fabrics” incorporating lithography-driven feature arrays limits designers’ ability to optimize individual devices. And the future is likely to bring still more complexity. One new frontier is the need to optimize circuits to minimize energy use according to the workload of the target application. Another is the potential for design innovation in trailing manufacturing processes. As he put it, there is nothing “lean” about designing for 14 nm silicon. Startups and new products may be able to reduce their initial costs by using older technologies to field test ideas, then switching to newer processes as demand grows.
All this and more are discussed in the full interview, coming soon.
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