The Other Side Of Device Scaling

Just because feature sizes can be shrunk, doesn’t mean they will be—or at least not by everybody.


The push to 10nm and 7nm is a relatively straightforward path in PowerPoint. In multiple presentations across the semiconductor industry, in fact, it has been portrayed as a straight line progression spanning decades.

While most chipmakers are aware that the cost per transistor has been increasing below 22nm, due to double patterning and the challenges in designing finFETs and dealing with dynamic power, they are less aware of the kinds of questions being asked on the back end. It now costs about $8 billion to $10 billion to build an advanced fab, and while some of the processing equipment can scale multiple nodes, it’s always more cost-effective to buy it for the latest node and not have to upgrade or retrofit it to multiple nodes.

Timing is everything in this world. No matter how you slice it, this is a very big investment with uncertain returns. The mobile market is huge and growing, but not all of those devices are using the most advanced processes anymore. In fact, an increasing percentage of chips used in smart phones are being built at 40nm and 28nm rather than at 16/14nm, and that percentage will likely rise as growth shifts to developing markets. At this point there is no other single sector that can generate those kinds of volumes using the same chip design, and that is creating a problem for foundries and equipment makers.

This is why there is so much uncertainty about what to call the next node, and what the next node will actually look like. Commitment on future processes carries a huge price tag, and with these kinds of numbers it has to be well thought out. Several years ago, when 16/14nm was the next node on the horizon, big foundries were saying that 10nm would be the real volume and not 16/14nm. They’re all now talking about 7nm, but maybe with a 10nm back-end-of-line process. No one knows for sure.

Committing to a node number is like playing a high-stakes game of poker and figuring out when to go all-in. There’s always a chance someone will raise the ante beyond that. There also are a bunch of other foundries sitting on the sidelines watching to see when might be the best time to join the game—or whether to push into another direction entirely.

While the potential returns may not be as high, running fully depreciated fabs and equipment at older nodes for an increasing number of narrowly defined markets such as automotive or analog is a much safer business proposition. Yields and processes are fully mature, and demand is growing. That demand is likely to increase even further when the IEEE completes its vertical market blueprints, more or less as a replacement for the ITRS road map to the next process nodes. That could make older processes increasingly attractive to the semiconductor equipment and manufacturing sectors.

Uncertainty is bad for large public companies, which have to answer to their investors on a quarterly basis. R&D at these companies typically runs in the low- to mid-double digits. While some of that advanced development is being offloaded to consortiums such as Imec in Belgium, the actual equipment and process development costs are still enormous. And at some point this becomes a balancing act between the best returns over the short and long term versus the risk associated with those returns.

And that leads to some interesting questions. How many companies will push forward, and will there be enough volume and sufficient yield to make it worthwhile? Where will they find the next economies of scale? Or, put more bluntly, who’s going to flinch next? And when they do flinch, will others follow or continue to push forward?