The Week In Review: Design

Physical verification; new libraries from Aldec; improving PVT subsystems; IEEE approves 1800.2 for UVM; power modeling donation.



Synapse Design acquired Asilicon, a design services firm based in Ranchi Jharkhand, India. Through the acquisition, Synapse Design adds a second design center in India and gains an additional 80 engineers. “The focus of the Ranchi office will be to provide lower-cost offshore design center services for our customer’s designs targeting 7- and 10-nm process technology,” said Satish Bagalkotkar, Synapse Design CEO. Terms of the deal were not disclosed.


Cadence unveiled a new physical verification signoff system featuring a massively parallel architecture combining a pipelined infrastructure with stream processing and demonstrated near-linear scalability on up to 960 CPUs. The Pegasus Verification System provides up to 10X faster DRC performance on hundreds of CPUs versus the previous-generation Cadence solution. The solution also offers native cloud support.

Aldec updated its verification platform, adding new functionalities and libraries aimed at verifying complex SoC, ASIC and FPGA designs. Improvements include 28% faster SystemVerilog random constraint simulation, 10% faster UVM simulation, and 3800% faster simulation for designs using VHPI interface.

Microsemi released updates to its suite of FPGA design tools, including mixed language simulation, new constraints management features and a new netlist viewer. The suite includes Mentor’s ModelSim simulator, as well as enabling the use of breakpoints in FPGA designs to improve visibility and reduce debug time.


UltraSoC and Moortec teamed up on SoC monitoring and analytics IP combining Moortec’s PVT sensor sub-systems with UltraSoC’s on-chip monitoring and analytics architecture. The companies say that their technologies will deliver a new generation of “smart” PVT sensors with local intelligence and features such as built-in preventive maintenance, load balancing to reduce failures and better control of power consumption for longer battery life.


The Universal Verification Methodology (UVM) was approved as an IEEE standard, IEEE 1800.2. The standard establishes a set of APIs that are used to define a base class library (BCL) definition for developing modular, scalable, and reusable components for functional verification environments. The APIs and BCL are based on the IEEE 1800 SystemVerilog standard. According to Lu Dai, Accellera Chair, the Accellera UVM Working Group will continue to provide improvements to the base class library implementation and updates to the UVM User’s Guide, while the UVM Language Reference Manual will become responsibility of IEEE. The standard will be made available at no charge through the IEEE Get Program.

Si2 contributed new power modeling technology to the IEEE P2416 System Level Power Model Working Group. The transfer is aimed at creating a standardized means for modeling SoCs designed for lower power consumption. According to Jerry Frenkil, Si2 director of OpenStandards, “This new modeling technology provides accurate and efficient, early estimation of both static and dynamic power, including critical temperature dependencies, using a consistent model throughout the design flow. There’s currently no standard way to represent power data for use at the system level, especially across a range of process, voltage and temperature points in a single model.” Organizations that contributed to the model development are:  ANSYS, Cadence, Intel, IBM, Entasys, and North Carolina State University.


Silicon Creations selected Mentor software for circuit, functional, and physical verification of pre-layout and post-layout analog and mixed-signal IP from 180nm to 7nm, including precision and general purpose phase-locked loops (PLLs), Enterprise class SerDes, and high-speed differential IOs.

Novatek adopted Synopsys’ Verification IP (VIP) and source code Test Suite for HDMI 2.1 and HDCP 2.2. Novatek cited the efficiency and performance of the VIP.

Mentor released a qualified reference flow comprising physical verification, physical synthesis, place and route, and test tools and flows optimized for Samsung’s 14LPP process technology.

Ansys announced that manufacturers have used Ansys tools to design, simulate, generate and test embedded code for over 100 qualified aerospace applications that have been certified under DO-178B and DO-178C.

In Memoriam

Robert Gardner, executive director of the EDA Consortium from 2007 until 2015, died April 11 at the age of 74 after a short illness. He was a member of the Board of Directors for Verific Design Automation since its inception in 1999. He co-founded Missing Link Electronics in 2008 and was its president and chief operating officer at the time of his death. Gardner held senior management positions at semiconductor and EDA companies Signetics/Philips, AMD, Exemplar Logic, Design Acceleration, Bridges2Silicon, and ITeX.