IP’s latest merger; IEEE President-Elect from EDA; VIP for LPDDR5; ARM IP for free (until commercialization); connectivity IP bundles; automotive instrument display software; IP legal advice.
Continuing to seek economies of scale in the IP industry, VeriSilicon and Vivante are combining forces. “This transaction creates an extensive semiconductor IP portfolio that will now include GPU cores, vision image processors, digital signal processors, video codecs, mixed signal IP and foundry foundation IP,” said Wayne Dai, VeriSilicon chairman, president and CEO. The merged company will continue under the VeriSilicon name, and terms of the deal were not disclosed. Interestingly, it remains a family affair: the two companies are headed by brothers.
Karen Bartleson has been elected as the 2016 IEEE President-Elect. Currently the Senior Director of Corporate Programs and Initiatives at Synopsys, Bartleson was President of the IEEE Standards Association in 2013 and 2014, and received the Marie R. Pistilli Women in EDA award in 2003.
Cadence unveiled its Memory Model VIP for the LPDDR5 standard, to verify that SoC designs are compliant with the JEDEC interface standard and that they can operate correctly in a system with the actual memory components.
ARM is offering free pre-commercialization use of Cortex-M0 processor IP, including system IP, peripherals, test bench and software, plus a 90 day license for Keil MDK development tools and access to low-cost FPGA prototyping. Developers wishing to enter full commercial production can purchase a simplified and standardized $40,000 fast track license.
Imagination presented the first of its complete IP subsystems, which combine Wi-Fi/Bluetooth software, media access control layer, baseband, analog front end and RF. The initial releases include a low-power Wi-Fi 802.11n 1×1 subsystem, an ultra-low power Bluetooth Smart and 802.15.4 subsystem, and a high-performance Wi-Fi 802.11ac 2×2 MIMO subsystem.
Mentor Graphics released its digital instrument cluster solution for automotive, which allows safety-critical and non-critical information to be displayed simultaneously on the same display, while maintaining isolation of safety-related functions to comply with ISO 26262 safety standards. The software architecture can be implemented on a multi-core or single-core SoC.
5-year-old systems startup Wave Semiconductor licensed Sonics’ flagship NoC product to integrate a massively parallel array of custom processing elements with third-party IP in its SoC design for machine learning and other compute-intensive applications.
Phison Electronics used Cadence’s power integrity solution to provide accuracy on electromigration and IR-drop checks for three silicon-proven designs for flash controller chips in the past 12 months. Phison says using the tool reduced its tapeout schedule by eight weeks, improving time to market by 40%, and increased overall product reliability.
The EDA Consortium is running a legal series of advice for IP vendors entitled, Patents and Patent Litigation: Strengthen and Protect Your Intellectual Property. The event will be held on Oct. 29 in the SEMI/EDAC offices.