Are Larger Reticle Sizes On The Horizon?

Making high-NA EUV lithography work will take a manufacturing-worthy approach to stitching together circuits from every two exposures or a wholesale change to larger masks.

Circuit stitching between the exposure fields is challenging the design, yield and manufacturability of the high-NA (0.55) EUV transition. The alternative is a radical change from 6×6-inch to 6×11-inch masks that would compensate for throughput losses with high-NA EUV, but that requires near-complete replacement of the mask-making infrastructure.

Modern multi-core SoCs with ever-larger amounts of on-chip memory often struggle to stay within the reticle limit, an area of 858mm² on 193nm immersion and EUV lithography, which shrinks to 429mm² for high-NA due to the anamorphic lens. Incorporating interposers into the package allows fabs to split such designs into chiplets, but the interposers still must fit within the standard field size. That size is determined by the reticle dimension (6×6 inches), which is shrunk by 4X by lithography scanners (up to 858mm²). For high-NA EUV, that field is half as large or 429mm², also halving the throughput of EUV tools. The result is that patterns on every two exposures must be stitched together.

Stitching multiple reticles to form a single design is becoming an important problem across multiple lithography regimes, said Christopher Bottoms, IBM researcher, speaking at the recent SPIE Advanced Lithography and Patterning conference. [1] Perhaps the most serious stitching challenge, however, comes from high-NA (0.55) EUV exposure tools.

In high-NA exposures, incident light strikes the reticle at a shallower angle. Because EUV optics are reflective, the incident light potentially can interfere with the refracted light before it reaches the wafer. Zachary Levinson, staff application engineer at Synopsys, explained that high-NA systems use anamorphic lenses to avoid the problem, with 4X demagnification in one direction and 8X in the other. Unfortunately, this solution cuts the field exposed by a standard 6×6-inch reticle in half, [^⁠2] which also halves the throughput.

Splitting a single circuit layer across multiple reticles immediately raises yield concerns, especially for critical layers that already have very challenging dimensions. In addition to the two halves of the design being precisely aligned with each other, they also must align with the full field layer above them. Levinson estimates that a 2nm mask-to-mask overlay error will lead to at least a 10% error in the pattern critical dimension, independent of any other sources of error.

Exposure tool stitching threatens yield
Advanced lithography depends on a variety of corrections to ensure accurate printing of corners, line ends, and other features. Assist features from both masks must be placed carefully to avoid interfering with each other. Any wafer feature that crosses the boundary between the two masks will be assembled from two different line segments. To combine the two into a single contiguous resist feature, both mask designs must account for both the overlap between the two line ends and their interactions with the boundaries of the two masks.

EUV masks include a black border, etched all the way through the multilayer stack forming the mask blank. This region prevents stray reflections onto adjacent exposure fields, but it also causes stress relaxation that distorts the immediately adjacent multilayer. Thus, an additional unpatterned blank area lies between the black border and the actual mask pattern. In a design printed “at-resolution,” by simply cutting it at the stitch line, the border region on Mask A overlaps the patterned area of Mask B. The effect on the aerial image depends on a number of factors, including the reflectivity of the mask absorber and the sensitivity of the resist.

Dongbo Xu and colleagues at Siemens EDA found that resist lines tended to narrow or become wider in the vicinity of the stitching boundary, depending on the amount of overlap. Contact holes gave even worse results, with either duplicate or oval holes.[⁠3]

Some degree of mismatch at the stitch boundary is unavoidable, said Synopsys’ Levinson, so it’s essential for designers to avoid placing critical features in the boundary area.

Stitching aware design threatens performance
The simplest solution, according to UCLA researcher Sagar Jain, is to exclude circuit features from the boundary area entirely.[^⁠4] Lines that might otherwise cross the boundary can be routed up to a full-field layer, across the exclusion zone, and then back down. As noted above, though, overlay between half-field and full-field layers is already challenging. Misaligned vias could threaten yield in this approach, and the increased length of the affected wires will impact performance. The results depend on the exclusion zone’s width and placement, as well as the number of high-NA EUV layers in the design. Worst case, single-core designs could see a 3% reduction in maximum frequency and a 3% increase in power dissipation. In multi-core designs, circuit macros might need several variants, with or without exclusion zone crossings, adding design and validation complexity.

Yongchan (James) Ban, senior director of engineering at Synopsys, and his colleagues, instead of excluding the boundary entirely, modeled a number of different stitching-aware design optimizations, all aimed at reducing the number of lines that cross the stitching boundary.[^⁠5] The first and simplest of these prevented logic blocks from being split across the boundary.

Next, the design placed related I/O ports near each other and in the same half field. These two options reduced the number of signal paths affected by the split, while clustering I/O ports reduced the overall line length, as well. Avoiding placement of standard cells near the boundary further reduced boundary crossings. Overall, these optimizations reduced the stitching area penalty to less than 0.5%, and performance degradation to about 0.2%.

While these changes reduce the number of features affected by the boundary zone, the features that remain still face printability issues. Region-specific design rules can help ensure that features near the boundary line will print correctly, Ban said. However, this approach is also more disruptive to the overall design. Standard cells might have different dimensions and therefore different characteristics depending on their placement and orientation relative to the boundary.

While stitching-aware optimizations will require careful modeling of lithographic behavior in the near-boundary region, the design community seems prepared to meet the challenge. The throughput impact, however, is unavoidable.

Bigger reticles eliminate stitching, bigger tool costs
Harry Levinson, president of HJL Lithography, estimates that halving the size of the exposure field could reduce throughput by as much as 40%, depending on the design. Moreover, much of the throughput cost is due to the field-to-field scanning overhead. If there are twice as many exposure fields, the scanner will have to increment twice as many times. Increases in source power or resist sensitivity will have relatively little effect.

However, increasing the reticle dimensions could solve both stitching and throughput challenges at once, as suggested by Frank Abboud, Intel vice president. In a presentation for the eBeam Initiative, he quoted ASML as saying their current EUV stage design can accommodate a 6×11.2-inch reticle with no changes to the optical elements. Mycronic, which already makes mask writing tools for the flat panel display industry, is prepared to have a prototype 6×11-inch mask writer as soon as next year.

Such optimistic pronouncements are far from the whole story, though. A reticle size change would affect every tool in the mask shop, from the deposition and inspection tools used to make blanks, to the resist coating and development tools for absorber patterning. Levinson counts 14 different pieces of equipment that would change. Even Abboud, an enthusiastic advocate for the larger mask size, acknowledges that it would double the cost of some tools.

EUV mask blanks pose a particularly difficult challenge, according to Aki Fujimura, CEO of D2S. Doubling the area would make already severe stress management and defect control challenges worse.

On the other hand, after many years of delays, EUV finally was adopted because of the very high throughput cost of DUV multi-patterning. EUV scanners already cost nearly US$400 million. Scanner productivity is the single largest contributor to overall fab cost efficiency. A larger mask size would save high-NA EUV scanners from dramatic productivity drops, Fujimura said, and it could dramatically boost the productivity of existing 0.33 NA scanners, as well. It would benefit devices well beyond the relatively small number of leading edge high-NA applications.

Though 6×11-inch masks are clearly a better option from a technical and throughput standpoint, the industry remains skeptical about their cost. Abboud pointed to the 1nm technology generation as a potential insertion point, as many tools will need upgrades to meet the requirements of that node anyway.

References

1. Christopher M. Bottoms, et al., “Multi-reticle stitching: applications from packaging to high-NA EUV,” Optical and EUV Nanolithography XXXVIII, edited by Martin Burkhardt, Claire van Lare, Proc. of SPIE Vol. 13424, 134240O doi: 10.1117/12.3051542
2. Zachary Levinson et al., “Full Field Stitching-Aware High-NA EUV OPC/RET Flow,” DTCO and Computational Patterning IV, edited by Neal V. Lafferty, Harsha Grunes, Proc. of SPIE Vol. 13425, 134250H doi: 10.1117/12.3052709
3. Dongbo Xu, et al., “OPC and Modeling Solution towards 0.55NA EUV Stitching,” Optical and EUV Nanolithography XXXVII, edited by Martin Burkhardt, Proc. of SPIE Vol. 12953, 129530K doi: 10.1117/12.3010519
4. Sagar Jain, Puneet Gupta, and Pieter Wöltgens, “Design Enablement of Low-Cost Stitching in High-NA EUV Patterning,” DTCO and Computational Patterning IV, edited by Neal V. Lafferty, Harsha Grunes, Proc. of SPIE Vol. 13425, 134250C doi: 10.1117/12.3051566
5. Yongchan (James) Ban, et al., “Mitigating Stitching-Induced Performance and Yield Losses in High- NA EUV Lithography: Place and Route Implementation Approaches,” DTCO and Computational Patterning IV, edited by Neal V. Lafferty, Harsha Grunes, Proc. of SPIE Vol. 13425, 134250D doi: 10.1117/12.3051175

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