ATE Market Changes With The Times

By Jeff Chappell
A declining PC market in recent years coupled with the continuing growth of mobile phones and tablets has meant changes throughout the semiconductor supply chain, and automated test equipment is no exception.

For example, a decade ago memory test—namely DRAM—was a large market compared with that of nascent system-on-a-chip (SoC) testing. In fact, at the time some test executives questioned the marketing hubub over SoCs. Of course the PC was still king at the time, even in a post-dotcom bubble world. Smartphones were still expensive and uncommon outside the business world while tablet computers were a rarity (and still thick and heavy).

By 2008 the SoC test market and the memory test market were essentially the same size, however, as the market for consumer devices continued to grow, led by handset growth.

In the ensuing years SoC test continued to outgrow memory test. Last year in 2012 the memory test market was $362 million, while the SoC test market was $1.7 billion, according to Mark Stromberg, a semiconductor ATE analyst with Gartner Inc. The company forecasts that the SoC test market will continue to outstrip that of memory: the memory market will hit $620 million by 2017, while the SoC test market will reach $2.85 billion. In fact at an annual growth rate of 2.5 to 3 percent between 2012 and 2017, the SoC test market is set to slightly outpace the overall market growth for semiconductor ATE.

While the overall memory test market may be declining in terms of annual growth, the use of NAND flash in all those phones and tablets has driven an increase in demand for NAND ATE. “NAND testers have really kind of accelerated nicely,” said Stromberg. “It’s a really strong market this year.”

As the markets for test have changed, so have the players. Like elsewhere in the semiconductor supply chain, today there are considerably fewer than there were a decade ago, as exits or mergers have reduced their numbers.

Viewed in terms of sales there are two major semiconductor ATE vendors, Advantest Corp. and Teradyne Inc., with LTX-Credence a distant third. Advantest, incidentally, completed its merger with Verigy (itself the former semiconductor test business previously spun out from Agilent Technologies) a year and a half ago; it debuted its first product developed since that merger last month at Semicon West, the T5831. Not surprisingly, Advantest is billing the T5831 as an advanced NAND tester, among its capabilities.

No Time to Lose
Of course some things never change. Cost-of-test, time-to-yield and time-to-market remain primary drivers, and likely always will for ATE. Each generation of tester seems to be able to test more devices in parallel than the previous generation. Today memory testers can test some 1,000 devices in parallel, while non-memory ATE and probe cards have evolved to test as many as 16 to 32 devices in parallel.

But mobile devices, which have given rise to the prevalence of not just SoCs and NAND flash but multi-chip modules and packages, are providing new challenges and drivers for ATE companies.

“The thing we are seeing becoming more important over the last two years is that our customers who are dealing with (their) Tier 1 customers, large handset manufacturers and computer manufacturers are beginning to institute really strict quality standards,” said Greg Smith, computing and communications business unit manager at Teradyne.

These customers are striving for extremely low defective parts per million (DPPM) levels, namely because these consumer driven markets move and react extremely fast. Customers playing in mobile consumer end markets often want to move from sample devices into volume production within the span of one quarter—just three months, noted Gary Fleeman, vice president of marketing at Advantest.

The fact that end markets react quickly is a factor, as well. Take for example the introduction of a new name-brand flagship mobile phone, such as a Samsung Galaxy or Apple iPhone, which will sell 100 million units within a few months of first hitting the market. Even with a relatively low DPPM of 100, that translates into 10,000 customers, observed Smith. Those customers will spread the news of their faulty device via the Internet and social networks.

“Because of how connected the world is, you can end up with these relatively low-rate problems becoming a big reputation problem,” he said, citing Apple’s notorious iPhone antenna issue. “All of these suppliers to Tier 1 developers of smartphones and tablets understand the asymmetric risk of a quality problem.” Thus those concerns filter down to ATE suppliers.

This pressure for low defectivity in a timely manner is a particularly peculiar issue, perhaps, for ATE vendors when dealing with NAND flash. Ubiquitous NAND devices have become so dense and complex, and manufacturing turnaround times so fast, that it’s virtually impossible to fabricate a perfect NAND device. It’s up to the related device controller to manage the errors.

This can lead to an unwanted increase in test times, said Ira Leventhal, senior director of R&D for Advantest’s Americas Memory unit. In response to this problem, the company designed its new tester, the T5831, to provide error-related analysis in the background while the device is in operation under test. The tester also features a real-time source-synchronous interface in which the device under test provides timing clock data to the tester while it is itself being tested.

Interconnects and stacked devices
While managing the ever-present time-to-market and test cost issues, ATE vendors also have to have a care for the near future. Current multi-chip modules and packages and stacked packages or 3D packaging are keeping ATE vendors on their toes. “This is the age of interconnect,” observed Advantest’s Fleeman. “Even conservative businesses like automotive (electronics) are moving into multi-chip packaging and multi-chip dies.”

While packages have gotten more complex and interconnects more dense, the end products they are going into keep getting smaller and thinner, which means the packages have to be thinner as well, and consequently more delicate. “It’s changing the handling environment,” Fleeman said. “Handlers aren’t sexy, they’re utilitarian, but we have to think about it,” he added. Thermal issues are also more prevalent than ever, thanks to more powerful devices in ever-thinner packages.

The need for dense interconnects coupled with the use of corresponding technologies such as copper micropillars are bringing further challenges, particularly for probe card makers. “Companies like Amkor are doing a good job of bringing dense contacts to the industry,” Fleeman said, noting a single device may contain some 10,000 to 20,000 delicate copper micropillars. “Contact is becoming quite challenging.”

Through-silicon vias (TSV) and 3D ICs are another potential headache for ATE vendors. “We’ve spent a fair amount of time thinking about it, but it is still very much up in the air,” said Teradyne’s Smith.

The attraction of TSV and 3D methodologies are the potential to create a device that contains stacked memory on top of a mobile processor, for example. Such a device would provide memory with lower power requirements yet larger bandwidth than what is possible today. “That’s the Holy Grail. That’s what people have been trying to achieve,” said Smith. While no one has achieved such a device just yet, the efforts have nevertheless driven a lot of innovation among memory makers.

And anytime you stack assemblies of devices before they are packaged together, the testing of said devices naturally gets complex. This is driving more test to be done at the wafer level to ensure the devices going into those assemblies and packages are good. The potential problem with multi-chip devices is that if one chip is bad, the entire device is bad. It’s also driving the expanded use of such test methods as boundary scan and built-in self test (BIST), which will require ATE to support such methods.

Then there is the need to test such a completed device or module as a system. “Imagine you have a baseband processor, RF chip, a power management chip, and some memory, and it’s all stacked into this complex 3D IC,” said Smith. “The best way to ensure quality is to perform all of those functions involved on all of the die at the same time, the equivalent of placing a call, browsing the Web, or sending a text message. It’s driven us to add features to our testers to communicate in the protocols of the devices in real time. We’ve developed our current generation of testers to handle this type of stuff.”

It’s still relatively specialized, and consequently small parts of the market that utilizes TSV and 3D ICs, such as MEMS and certain image sensors. But as for highly complex digital devices using these technologies, “We’re still waiting for that to emerge as a real factor,” Smith said.