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Ann Mutschler

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Ann Mutschler is senior executive editor at Semiconductor Engineering.

Author's Latest Posts

The Growing Software Challenge: From Stacks To SMP
By Ann Mutschler - 26 Aug, 2010 - Comments: 0

By Ann Steffora Mutschler Building a system now includes software, but defining the software stack is a mounting challenge for engineers. What used to be almost exclusively drivers now includes RTOSes and OSes, executable files, middleware, firmware, IP, embedded software and applications. With millions of different embedded products, all with different sets of software, it comes down to pr... » read more

Extending Moore’s Law
By Ann Mutschler - 26 Aug, 2010 - Comments: 0

By Ann Steffora Mutschler For Moore’s Law to perpetuate, the materials used in semiconductor manufacturing must do their part to allow the scaling of devices to occur. Some of the latest include a carbonless film deposition technology for 20nm transistors and smaller, a plastic memory device and a material compound of silicon, copper, nickel and iron that researchers believe could lower manu... » read more

iPhone Has The Power Blues
By Ann Mutschler - 12 Aug, 2010 - Comments: 0

Why do some apps on the iPhone seem to draw more on the battery than others? Is it a matter of power-aware software applications, or is it a hardware issue? Maybe it is a combination of both. I suspect it is due to the intricacies of hardware/software design and verification. I’ve been mulling this over while researching my two articles for this month’s issue of Low-Power Engineering... » read more

Why Open Source Matters
By Ann Mutschler - 22 Jul, 2010 - Comments: 0

By Ann Steffora Mutschler A huge effort has been under way to create virtual prototypes that allow true hardware/software co-design, but there are still a number of pieces missing. One significant missing element is a full library of IP models to guide the process, and the solution could come from an unlikely place—open source developers. Today, ‘open source’ IP generally seems to be ... » read more

ESL Requires New Approaches To Design And Verification
By Ann Mutschler - 22 Jul, 2010 - Comments: 0

By Ann Steffora Mutschler As more data gets front loaded into SoC architectures today, understanding verification challenges as well as communication between the front and back end has never been more critical. “All of this is getting more complicated,” said John Ford, director of marketing at ARM. “There was a time when an ARM processor core was all that was on a chip. Now there’s ... » read more

Power Makes IP Integration More Fun
By Ann Mutschler - 08 Jul, 2010 - Comments: 0

Remember the good old days at 130nm when it was easy to combine IP blocks on an SoC? All kidding aside, because obviously IP integration has always had its challenges, designers are experiencing new pain as process, voltage and temperature wreak havoc in bringing everything together and making sure it operates correctly, meeting all power requirements. As I discovered, whether IP comes from ... » read more

End User Report: EDA Industry Realignment
By Ann Mutschler - 24 Jun, 2010 - Comments: 0

By Ann Steffora Mutschler The EDA industry has seen a number of large acquisitions as of late, most notably of Denali by Cadence, as well as CoWare, VaST and Virage Logic which were acquired by Synopsys, but just what impact does this realignment have on the biggest EDA customers? Commenting on these changes is Jean-Marc Chateau, director of system platforms and tools at STMicroelectronics, ... » read more

Connecting The Pieces
By Ann Mutschler - 24 Jun, 2010 - Comments: 0

By Ann Steffora Mutschler With the amount of IP blocks being integrated in SoCs today – in some cases as many as 100 blocks in a single chip – SoC design methodologies are shifting to address the new challenges this complexity brings. The good news is that these integration challenges has put the spotlight on the issues—along with the skyrocketing development costs for the creation, qual... » read more

Giant Steps—Backward
By Ann Mutschler - 10 Jun, 2010 - Comments: 0

With DAC headlining next week, power is sure to take center stage given its prominence as a key pain point for design engineers that are always on the lookout for a new technique to ease their power management burdens. In many low-power designs, asynchronous technology may be just the thing. One of the biggest disadvantages of the clockless CPU is that most design tools assume a clocked CPU ... » read more

TLM 2.0: Necessary for Co-Simulation
By Ann Mutschler - 27 May, 2010 - Comments: 0

By Ann Steffora Mutschler Transaction-level modeling – an abstracted representation of design IP above the RT level -- continues to grow in importance for architectural exploration, performance analysis, building virtual platforms for software development, and functional verification. The TLM-2.0 standard is the current industry standard for creating interoperable transaction-level models an... » read more

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