Mark LaPedus

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Mark LaPedus is Executive Editor for manufacturing at Semiconductor Engineering.

Author's Latest Posts

Wanted: New Metrology Funding Models

By Mark LaPedus - 21 Mar, 2013 - Comments: 0

By Mark LaPedus The shift toward the 20nm node and beyond will require new and major breakthroughs in chip manufacturing. Most of the attention centers around lithography, gate stacks, interconnects, strain engineering and design-for-manufacturing (DFM). Lost in the conversation are two other critical but overlooked pieces in the manufacturing puzzle—wafer inspection and metrology. ... » read more

Reaching For The Reset Button In Lithography

By Mark LaPedus - 21 Mar, 2013 - Comments: 0

By Mark LaPedus Amid ongoing delays and setbacks, extreme ultraviolet (EUV) lithography and multi-beam e-beam have both missed the 10nm logic node. So for the present, chipmakers must take the brute force route at 10nm by using 193nm immersion with multiple patterning. Now, it’s time to hit the reset button. For the 7nm node, chipmakers currently are lining up the lithographic competition... » read more

Making An Impression with Nanoimprint

By Mark LaPedus - 21 Mar, 2013 - Comments: 0

By Mark LaPedus Semiconductor Manufacturing & Design sat down to discuss the trends in lithography with Mark Melliar-Smith, president and chief executive of Molecular Imprints Inc. (MII), a supplier of nanoimprint lithography tools. SMD: How do you view the IC industry now? Melliar-Smith: It’s truly incredible work that this industry continues to do. The industry will see its way f... » read more

Directed Self-Assembly Grows Up

By Mark LaPedus - 21 Mar, 2013 - Comments: 1

By Mark LaPedus At last year’s SPIE Advanced Lithography conference, Christopher Bencher, a member of the technical staff at Applied Materials, said the buzz surrounding directed self-assembly (DSA) technology resembled the fervor generated at the famous Woodstock rock concert in 1969. This was clearly evident from the tumultuous and free-flowing movement that threatened the status quo o... » read more

Getting Ready For High-Mobility FinFETs

By Mark LaPedus - 21 Feb, 2013 - Comments: 0

By Mark LaPedus The IC industry entered the finFET era in 2011, when Intel leapfrogged the competition and rolled out the newfangled transistor technology at the 22nm node. Intel hopes to ramp up its second-generation finFET devices at 14nm by year’s end, with plans to debut its 11nm technology by 2015. Hoping to close the gap with Intel, silicon foundries are accelerating their efforts t... » read more

Foundry Arms Race Under Way

By Mark LaPedus - 21 Feb, 2013 - Comments: 0

By Mark LaPedus A year ago, chipmakers were reeling from a severe shortage of 28nm foundry capacity, prompting foundries to ramp up their fabs at a staggering pace. At the time, foundries were unable to keep up with huge and unforeseen demand for mobile chips. The shortfall was also caused by low yields and the overall lack of installed 28nm capacity. Today, the 28nm crunch is largely ov... » read more

Optical Lithography, Take Two

By Mark LaPedus - 21 Feb, 2013 - Comments: 0

By Mark LaPedus It’s the worst-kept secret in the industry. Extreme ultraviolet (EUV) lithography has missed the initial stages of the 10nm logic and 1xnm NAND flash nodes. Chipmakers hope to insert EUV by the latter stages of 10nm or by 7nm, but vendors are not counting on EUV in the near term and are preparing their back-up plans. Barring a breakthrough with EUV or other technology, IC ... » read more

Multicore Madness

By Mark LaPedus - 21 Feb, 2013 - Comments: 0

By Mark LaPedus Smartphones and tablets are migrating towards new and faster application processors, basebands, graphics chips and memories. In the cell-phone chipset area alone, there are a multitude of options and design considerations. Some devices combine the application processor and modem on the same chip. Some are separate devices. In addition, the architectures range from single- to... » read more

What Will Replace Dual Damascene?

By Mark LaPedus - 24 Jan, 2013 - Comments: 0

By Mark LaPedus In the mid-1990s, IBM announced the world’s first devices using a copper dual damascene process. At the time, the dual damascene manufacturing process was hailed as a major breakthrough. The new copper process enabled IC makers to scale the tiny interconnects in a device, as the previous material, aluminum, faced some major limitations. Dual damascene remains the workhorse... » read more

Inside The Package

By Mark LaPedus - 24 Jan, 2013 - Comments: 0

By Mark LaPedus Semiconductor Manufacturing & Design sat down to discuss IC packaging trends with Rich Rice, senior vice president for North America at Taiwan’s Advanced Semiconductor Engineering (ASE), the world’s largest independent IC packaging and test house. SMD: Amazingly, there are still more than 100 vendors competing in the IC test and assembly business today. But for year... » read more

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