Expensive DUT interface boards complicate development and operations.
Parallel test is used for nearly every device produced by fabs and OSATs, but it can reduce yield and increase the cost of test boards and operations.
This is a well-understood tradeoff for ensuring consistent test accuracy across multiple sites and reducing test time. Collectively, ATEs and multi-site test boards — DUT interface boards (DIBs), probe cards, and load boards — significantly reduce test time. But effectively addressing the power integrity, signal integrity, and co-planarity specifications requires more PCB layers, more components, and at times, electro-mechanical relays, all of which add to the cost. In addition, highly parallel test boards can negatively impact yield and increase the cost of manufacturing.
To begin with, multi-site test board design considers ATE resources and handling limitations. “The load boards follow the standards dictated by the tester on one side, and by the handler on the other side,” said Nicolas Cathelin, business development manager of automation and interface solutions at Advantest Europe. “Nevertheless, as parallelism increases with large I/O count devices, the number of loadboard layers may increase above 100, and costs increase proportionally. This may affect the cost of test (CoT) per DUT, and we carefully consider this together with our customers to provide the optimal solution,”
Meeting the mechanical design specs is just as important as meeting the electrical specifications. The mechanical force needs to be applied evenly across all points of contact, which requires co-planarity between the test board and device under test. More DUTs to test at one time means more surface area to align. This makes it more difficult to meet co-planarity specifications, which in turn affects contact resistance and causes yield loss.
Multi-site DUT interface boards, in addition to being expensive, can affect overall equipment effectiveness (OEE), or the percentage of time a tool spends processing actual devices. Test floor managers seek to balance product throughput, yield, and cost of ownership. Engineering teams must determine tradeoffs between running cleaning recipes versus retesting and boosting yield, while also managing test board repairs. Such choices impact yield and throughput. Put simply, decisions on the number of test sites have consequences on the factory floor. And just because one can successfully design a DIB with 128 test sites does not mean it’s the best operational decision with respect to manufacturing cost.
Fig. 1: Multi-site test board design effects on test floor. Source A. Meixner/Semiconductor Engineering
The test chapter of the Heterogeneous Integration Roadmap [1] highlighted that increasing yield by 1% can reduce overall manufacturing cost by 9%. In comparison, implementing four individual test cost reduction methods each reduced manufacturing cost by less than 2%. Thus, while increasing the number of devices tested in parallel can increase throughput and lower costs, any corresponding impact on yield needs to be considered.
Design expenses
To fully understand the test board costs in the context of parallel test, one needs to start with the electrical design and validation process. As engineers increase the number of DUTs, test board real estate becomes precious. Using smaller components for passives, relays, and surface-mount technology solves the real estate limitations, but it drives up the cost.
Using more board layers also raises costs, but it’s essential with multi-site test boards. Consider a hypothetical case of 500 signals and 1,000 power interconnects to route for a DUT. Increasing that to 8 DUTs results in 12,000 traces routed to meet the identical signal and power integrity specs for one DUT. Increasing board layers enables the distance, spacing and isolation for routing.
“In parallel test, the signals from multiple sites are tested simultaneously, which increases the likelihood of cross-talk and noise interference, said Masood Ahmad, senior global applications engineer manager at Advantest. “In a crowded design, high-speed I/O routings are more susceptible to crosstalk and interference. This degrades signal integrity. It is also difficult to route signals with matched length while maintaining symmetry across sites. Optimized routing techniques are used — maintaining signal isolation using required trace spacing and proper grounding to minimize noise and crosstalk — as well as using multi-layers to isolate signals.”
Engineers need to consider similar design challenges for power delivery networks.
“As the number of distinct voltage rails increases, the load board complexity will also increase — sometimes significantly,” said Michael Keene, senior systems engineer at Teradyne. “In these cases, tradeoffs often must be made between load board stack-up, layer counts for ground and power nets, bypassing, and power plane routing in order to achieve adequate power integrity (PI) for each DUT circuit.”
As test board cost and complexity climb, so does the need to validate them prior to deployment in a production setting.
“The front-end cost is often neglected from the back-end purview, and vice versa,” said Craig Force, semiconductor test automation specialist at Emerson Test and Measurement. “We’ve had multiple customers say their test boards are about a million dollars for one product. This includes validation all the way out to production. Now we’re getting to the place where we’re looking at the cost of test boards approaching mask set costs. What is the cost of that load board if I didn’t validate that load board properly? It’s a $150,000 to $200,000 frisbee that you throw away. I don’t want to call them hidden costs, but there are costs associated with the development activity before rolling out to production. Multiple iterations may be required to get it right.”
Yield and throughput
As board costs grow with each additional test site, so do the deployment costs on a test factory floor. When measured in terms of yield and throughput, deployment costs can drive a lower amount of parallelism.
Test board mechanical properties, and the choice of appropriate contactor pins or probe tips, also can impact alignment (x,y) and co-planarity (z). Successfully meeting the associated specs results in low contact resistance. Parallel testing increases the surface area, and hence increases the difficulty in achieving physical contact specs. With higher multi-site counts than final test, wafer probe card design becomes significantly harder.
“There are mundane things, like stiffness of the interface,” said Kevin Manning, system engineer at Teradyne. “To test a bunch of parts at once, you apply a lot of force against the tester. Mechanical stiffness impacts planarity when applying such forces. This is especially a concern at wafer probe. High site count drives large probe arrays, and the larger your array, the more important it is to be parallel to the wafer. If you’re not parallel to the wafer then contact resistance is affected.”
Advantest’s Ahmad concurred with the criticality of probe card design. “In parallel test, probe alignment and planarity is more complex,” he said. “Keeping planarity between probes and pads is critical. Any misalignment can cause weak or open connections. Solutions include designing the probe card with precise alignment, and using MEMs-based probes. Both provide better alignment and contact reliability across all sites.”
With a potential 1% yield improvement, a test operations team has a vested interest in yield recovery via retest. Based upon lowering contact resistance, the retest plays out one of two ways. One approach uses greater mechanical force (e.g. overdrive during wafer probe) at contact. In the other, a cleaning cycle is used to clear debris from probe tips and pogo pins prior to retesting. The balance of these options and the additional test time creates a three-way tug-of-war when choosing to retest.
“The practice of online retest within a wafer/unit lot impacts test efficiency, especially at probe, where heavy-multi-site application are often implemented, said Davide Appello, vice president for the center of excellence at Technoprobe. “For example, the factory floor managers and their team need to create an optimized probe recipe, which balances the possible yield loss due to poor contacting issues and accounts for the extra test time necessary to yield recovery.”
At final test, another operational cost involves the mechanics of handling packaged parts. A handler picks up N DUTs to be placed in N sockets on a test board. After it aligns to the sockets, the handler applies sufficient force to push all parts against the sockets. Thus, as the number N becomes large, the challenges for alignment and co-planarity increase.
“Handlers have jam rates,” said Teradyne’s Manning. “If there’s a socket that they think is suspect, they turn it off, because they don’t want to take the machine apart and bring the whole tester down for one site. If you use huge handler with 1,000 sites, and then they start jamming, that represents downtime that affects a high throughput. You don’t want to necessarily dedicate all your throughput, or a large percentage of your throughput, to one machine. If you can have it more distributed, you’re less exposed to test inefficiencies.”
Considering throughput can thus lead to lower levels of parallelism.
Additional factors affecting a product’s throughput on the test floor include the needs for spare boards and board repair. DIBs are a consumable. Over time they become damaged or wear out, which necessitates repair or replacement. To avoid a line-down situation, at least one spare board must be available, and product volume often dictates more than one spare board. Also, high levels of parallelism translate to longer test board repair times.
Summary
As test sites multiply, the DUT interface board (a.k.a. test board) becomes more expensive, and complexity increases for managing the electrical and mechanical design specifications. This has ramifications for yield, throughput and cost of operations. So, while engineers can design very high multi-site test boards, the operational costs on the factory floor encourage scaling back those lofty expectations of very high parallelism.
Reference
Related Reading
Promises and Perils of Parallel Test
Test costs may be reduced, but how much depends on a whole bunch of factors.
Cleaning Up During IC Test
Dirty probe tips and sockets adversely affect test, which can impact chip reliability.
Managing Wafer Retest
Dealing with multiple wafer touchdowns requires data analytics and mechanical engineering finesse.
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