Weighing the tradeoffs of macro- and micro-inspection, and a combination of both.
Wafers can be inspected for large, obvious defects, or for small, subtle ones. The former is referred to as macro-inspection, while the latter is micro-inspection. These processes use different machines with different capital and operating costs, and they might look like competing approaches with different economic returns. In fact, they are complementary tactics that can be balanced within an overall strategy of optimizing yields, reliability, throughput, and investments.
“All customers want to have the best resolution [of micro-inspection], together with the high speed of macro-inspection,” said Dr. Thomas Fries, founder and CEO of FRT, a FormFactor company. “Of course, this does not work. Nevertheless, we and others are continually trying to speed up high-resolution measurements.”
Fabs routinely use both to find the best yield and reliability results for the lowest overall cost. Each fab determines its own best strategies for combining the approaches. There is no one right answer about the best way to do that.
Inspection investment and payoff
Wafer inspection would, at first glance, appear to be a requirement. If you want to make sure some operation was done correctly, simply inspect to confirm that it’s so. But in a commercial wafer fabrication facility, economics is a critical consideration and inspecting wafers doesn’t come for free.
There are numerous associated costs:
With all of these costs, there has to be a payback for it to make economic sense. The reasons for doing inspections at all can be summarized in two ways. One is rescuing or rejecting troubled lots before any further resources are spent on them. The second is getting an early warning when machines are drifting or operating outside of their normal bounds, thereby preventing additional lots from being mis-processed.
The primary goal is to improve fab operations for overall higher yields, ensuring that fatally flawed lots never make it to test and that, when possible, flawed lots can be reworked.
These days, however, all test, inspection, and monitoring operations have second- and third-order goals. Rather than just providing better yields during test operations, they also help to predict the future reliability of chips, making it possible to scrap borderline devices that might result in an eventual product return or, worse yet, a recall. While in-field failures are an obvious issue for safety-critical applications, they also can cause costly unexpected errors in other markets like data centers. “Those data center guys care about reliability defects almost as much as the automotive space,” noted Andrzej Strojwas, chief technologist at PDF Solutions.
Given a broad set of associated costs and benefits, the question becomes one of optimizing the way inspection is done for the best possible cost-benefit outcome. There’s no one right approach to this, and each fab management team may make different tradeoffs for what they believe to be the most effective inspection strategy.
Broadly speaking, there are two types of defects — random and systematic. As defined for wafer inspection, random defects could occur anywhere at any time. Fabs work hard to reduce their incidence, and their prevalence is usually measured in ppb. “It is virtually impossible to detect 100% of random defects using micro-inspection for all wafers, even with enough sensitivity,” said Strojwas.
This is becoming more difficult at every node, as well as with more heterogeneous designs “A typical high-end product would have tens of billions of transistors or contacts on each die,” said Indranil De, vice president of design for inspection at PDF Solutions. “So the failure rates have to be around 0.01 ppb for wafers to yield reasonably.”
Systematic defects follow some pattern. They’re still rare, but they can be three orders of magnitude more prevalent than random defects. “With systematic defects, parts per million detection rates are sometimes sufficient,” said Strojwas.
In fact, once random defects are reduced to a certain low level, what remains of them could turn out to be systematic. “The fab must first bring those random fail rates down,” said De. “That’s the first step. And then you may still find that, in certain systematic configurations, things fail more and cause certain products not to yield well. So then you would go around chasing these systematic failure issues.”
In search of defects
The purpose of inspection is simply to find defects or deviations from process targets. Exactly how that’s done depends strongly on the type and size of the defects. Many defects will be obvious, such as fall-on particles, dies damaged at the edge of the wafer, and residual substances after a cleaning operation are examples.
Fig. 1: A micro-inspection tool. Source: KLA
Others occur at the nanometer level. “Micro-defect inspection systems use either optical or electron-beam technology and are designed to find small defects – defects that are about the same size as the design rule of the devices being manufactured,” said Mark Shirey, vice president of inspection customer engagement at KLA.
By definition, critical-dimension (CD) measurements will look for deviations of nanometer-sized features, which means those deviations will be exceedingly small. Checking for edge-placement errors (EPE) may require looking through more than one layer to ensure that multiple photolithography steps precisely stack atop each other to provide sharply defined features.
Finding these minuscule defects can be extraordinarily difficult. Some defects become visible only if illuminated by an appropriate color, or wavelength, of light. Images may need to be processed to reveal a defect either for visual review or for automatic classification of the defect.
In addition, it gets harder to zero in on defects involving 3D structures. “Any kind of three-dimensional structure is going to distort a projected pattern,” said Tim Skunes, vice president of R&D at CyberOptics. “If you look at a two-level test target (see fig. 2), the center area and these wings are little depressions that are 1.5 to 1.8 microns deep. Because we’ve projected from the right side to the left, when viewed from the left it appears the structured pattern has shifted (see fig. 3). So there are three unknowns at each pixel. Z height varies by the phase, or how much that light has shifted. And then, when you have heterogeneous packages and different materials, reflectivity and fringe contrast change.”
Fig. 2: Projected image of 3D structure. Source: CyberOptics
Fig. 3: Projected image close-up showing shift. Source: CyberOptics
Lithography wavelengths add another variable, as well. While eliminating all defects is a good goal, the reality is that a defect in a mask or on the photoresist on a wafer is only a problem if it will print on the wafer. Photolithography exposure uses a specific wavelength of light. If the defect is not visible at that wavelength, then it won’t print and there will be no measurable effect on the wafer.
This suggests such inspection steps should be done only at the wavelength of photolithographic illumination – otherwise known as “actinic” inspection. But that’s not always easy. Providing actinic inspection for EUV illumination has posed a challenge and has focused mostly on mask inspection, which doesn’t affect wafer throughput.
Building recipes
As a result of the complicated and delicate nature of micro-inspection, it’s not possible to have one single approach to every wafer at a given silicon process node. Part of preparing a new die for fabrication includes identifying a “recipe” for inspection. “These recipe settings include optical parameters (wavelength range, focus offset, magnification, etc.), care area definition (designation of the die areas that will be inspected), and image processing algorithm parameters (thresholds, rules for automatic defect classification, etc.),” said Shirey.
Each inspection stop will have a recipe for each die. While some recipe “ingredients” may be found in many different recipes, it’s unlikely that two dies will share an identical recipe. “A unique recipe will be used for a particular device and process layer,” said Shirey. “In general, each inspection step has its own recipe.”
Recipes are critical to successful micro-inspection. “An inspection recipe plays a key role in determining what defects are detected and how many defects are detected,” said Shirey.
Still, managing recipes can be a fair bit of work. Each inspection step needs a recipe, making for a suite of recipes for each die. Those recipes will be created before manufacturing starts, but they may need to be tweaked and refined as experience leads to improvements in the recipes. So recipes themselves are an investment in time, making it important that they provide good results.
Each micro-inspection step will take some time to complete. But it’s not just the inspection time itself that’s of concern. “Fabs are more interested in how quickly they can obtain the defect information needed to determine the source of defects, to make decisions regarding wafer dispositioning, and/or to take corrective action on relevant processes or process tools,” noted Shirey.
The economics are further challenged by the cost of the equipment. “While these tools are very good at finding the subtle defects that affect device performance – defects that often cannot be found by other inline techniques – they can be more expensive in terms of capital and running costs,” said Shirey. Yet writing off such inspection as taking too long would mean forgoing the benefits of micro-inspection. So micro-inspection is done on a sample basis.
As more chips are packaged together, and as more 3D elements are added onto dies, other techniques will be required. Skunes, said some form of confocal technique will be required in the future. That approach captures multiple 2D images at different depths and reconstructs them into 3D structures.
“Most of the confocal techniques right now are two to three orders of magnitude too slow for inspection,” said Skunes. “So they’re 100 to 1,000 times slower than where we are today using our triangulation technology. We’re going to have to figure out how to innovate in that particular area and take those techniques to speed them up.”
He noted that improvements in inspection tend to be quantum leaps rather than simple evolutions. “High-speed CMOS imaging was a game changer, and within the last 10 or 15 years that’s really become mainstream,” he said. “We went from CCD (charged-coupled device) technology to high-speed CMOS when nobody thought CMOS technology was going to be good enough for imaging. So there’s high-speed CMOS imaging, digital projection technology, and more recently, with the advent of GPU technology becoming commercially available, for not a lot of money you can get an amazing amount of compute power.”
That can have a big impact on coverage and accuracy. But there also are other variables to consider, such as where the inspection is done in the lifecycle of a particular wafer. Shirey said that when doing analysis of engineering experiments, all of the wafers in the experiment will be inspected. When bringing up a new line or design, he suggests 2 to 3 wafers per lot on 20% to 30% of lots as typical, while ongoing monitoring would involve 2 to 5 wafers/lot from up to 100% of lots.
PDF Solutions cited a similar approach for its e-beam micro-inspection tool. “Typical wafer sampling might be 2 to 3 wafers out of 25-wafer lot,” said De. “And on each wafer we could target 30% to 50% of die area.”
Of key value, however, is the fact that micro-inspection compares wafers against an objective reference, and it can track multiple lots over time to reveal equipment drift that might otherwise go unnoticed. This allows both for equipment adjustments before they cause yield problems and for the possible feeding forward of results so that subsequent processing steps can be adjusted to compensate.
Identifying big defects may be easier
While micro-inspection has the capability of detecting tiny defects, it may be overkill for large defects. If the only inspection mechanism is micro-inspection, then only systematic macro defects will be found, since not every wafer is inspected. This suggests that complementary inspection tactics could identify those larger defects more cost-effectively.
This is the regime of macro-inspection. With this approach, there will be an acknowledged limit to the size of defect that can be detected. But the tradeoff is such that, if inspection is fast enough, every wafer can be inspected. Now you’re not just looking for defects as an indicator of something else going wrong. You’re using the defects themselves to make decisions about specific wafers and dies.
“Some fabs have chronic problems that come occasionally,” said Mike LaTorraca, chief marketing officer for Microtronic. “[Macro-inspection] can help, since you see every wafer,”
If a particular die has a problem on an otherwise acceptable wafer, then that information can be stored for pre-inking the die and skipping the testing, which speeds the testing process. Inspections following wafer test, such as after wafer bumping, also can result in post-inking so that the affected die won’t be packaged or further tested after assembly. Pre- and post-inking can be done using virtual die maps instead of physical ink.
While macro-inspection also can make use of recipes, Microtronic has an approach that operates without recipes. It relies on cameras that image the wafer and capture defects large enough to be visible within the camera’s resolution. Many pieces of equipment already have cameras – some of them unused, so they can make use of those. Or they can install a camera setup, perhaps where the wafers exit the machine.
In order to define a reference, operators select one wafer in a lot. That reference wafer is imaged, and then every other wafer in the lot is compared to that wafer. Visible deviations will be flagged as potential issues. If the reference wafer turns out to have issues, then most or all of the rest of the wafers will be tagged as having problems. Those problems would be the result of the reference wafer not being clean, and the system can’t know that in advance. This is where manual review is useful. The reviewer can immediately see what the issue is and disposition things appropriately. The reviewer also will classify any defects that can’t be classified by automatic AI techniques.
But this reveals an important aspect of this approach — it has no objective reference to compare to. The reference wafer becomes a relative reference, and it’s used only for that lot. Each lot will have its own reference, and all of the non-reference wafers will be judged relative to their reference. So each lot becomes independent, with wafers within the lot compared only to each other.
The benefit is that there is no operational dependency on a particular wafer or die design. All wafers for all designs at any stage of fabrication are handled in the same manner. Differences between designs are subtracted out by the use of the reference wafer. Notably, this means that no recipes are used.
Fig. 4: Macro defects detected on a wafer. Source: Microtronic
The lot-relative nature of such macro-inspection also means, however, that one can’t necessarily do lot-to-lot comparisons unless a reviewer happens to notice similar effects on multiple lots. One may be able to find specific equipment excursions, but not gradual lot-to-lot drift.
One concern might be that a systematic problem would give all of the wafers in the lot the same defect – and that this would render the problem invisible. But Microtronic said that there are likely to be small variations in how the defect presents itself from wafer to wafer and that those small differences can be enough to spot the issue.
Macro-inspection, then, provides a number of benefits:
Micro-inspection has its own benefits:
This allows the two types of inspection to act in a complementary fashion. “Macro defect inspection systems may not be able to find the smallest defects, but they can capture yield-related defects while operating at higher productivity, allowing fabs to screen for ramp or production excursions in a cost-effective manner,” said Shirey. “Fabs often deploy several types of macro-inspection screening at steps in between the most critical micro inspection steps. Used in this way, micro- and macro-defect inspectors are like a two-level safety net, ensuring that the most critical defects and large excursions are detected in a timely and cost-effective manner.”
LaTorraca provided a simple analogy. He said it’s like telescopes and microscopes, which don’t compete with each other. “We’re making a telescope, not a microscope,” he said.
In addition to having individually designated micro- and macro-inspection steps, they also can be combined, with macro-inspection providing early indications of further micro-inspection that might be warranted. “One solution is to do 100% full-speed macro-inspection combined with a fixed pattern of high-resolution measurements on the same wafers or on random wafers,” said FRT’s Fries. “The other option is to look on the fully inspected wafers for hints in the macro results and zoom specifically down into those areas. This is easiest to do in the same (multi-sensor) tool, as the respective positions are easily found.”
But speed expectations typically result in the micro-inspection follow-up being taken offline. “The throughput is slowed down by the high-resolution inspection, and it is more efficient timewise to use a second tool for going for the details,” Fries added.
Most inspection-equipment companies say both micro- and macro-inspection are necessary and that they work in a complementary fashion. How much of one or the other should be done becomes part of the optimization process that each fab will perform in order to dial in the best yield results for an acceptable amount of effort.
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