Chip Industry Technical Paper Roundup: Oct. 21


New technical papers recently added to Semiconductor Engineering’s library: [table id=484 /] Find more semiconductor research papers here. » read more

Research Bits: Oct. 21


Direct patterning with UV cross-linking Researchers from Ulsan National Institute of Science and Technology (UNIST), Yonsei University, Sungkyunkwan University, University of Chemistry and Technology Prague, and Sogang University developed a technique that enables the direct patterning of 2D semiconductor materials onto substrates without the use of toxic solvents. The process involves disp... » read more

Understanding and Mitigating Column-Based Read Disturbance in DRAM Chips (ETH Zurich, CISPA)


A new technical paper titled "ColumnDisturb: Understanding Column-based Read Disturbance in Real DRAM Chips and Implications for Future Systems" was published by researchers at ETH Zurich and CISPA. Abstract "We experimentally demonstrate a new widespread read disturbance phenomenon, ColumnDisturb, in real commodity DRAM chips. By repeatedly opening or keeping a DRAM row (aggressor row) ope... » read more

Microarchitectural Defense Strategy Against EM Side-Channel Attacks (Northeastern Univ., Binghamton Univ.)


A new technical paper titled "ShuffleV: A Microarchitectural Defense Strategy against Electromagnetic Side-Channel Attacks in Microprocessors" was published by researchers at Northeastern University and Binghamton University. Abstract "The run-time electromagnetic (EM) emanation of microprocessors presents a side-channel that leaks the confidentiality of the applications running on them. Ma... » read more

In-System Test For AI Data Centers


Testing inside the fab or packaging house can determine whether a chip or package meets all the functional requirements at time zero, but how that chip behaves in the field during its lifetime and under different workloads and environmental conditions may be very different. This is particularly true in AI data centers, where utilization of one or more dies may be significantly higher than in pr... » read more

AI Bubble Or Boom?


Are we in an AI bubble? Parallels are being drawn to the dot.com boom/bust of 1999-2000. In the dot.com bust, many high-tech companies valuations soared up 10X, then deflated. The peak P/E ratio for the Nasdaq Composite was 200! Remember Webvan? It went public November 1999 with an $8 billion valuation, then filed for bankruptcy 19 months later. It was much speculation without profits or gro... » read more

3D Stacked HBM and Accelerators for LLMs: Heat Management and PDN (Georgia Tech, SK Hynix)


A new technical paper titled "3D Stacked HBM and Compute Accelerators for LLM: Optimizing Thermal Management and Power Delivery Efficiency" was published by a researcher from Georgia Institute of Technology and SK Hynix. Abstract "Advanced packaging is becoming essential for designing hardware accelerators for large language models (LLMs). Different architectures such as 2.5D integration of... » read more

Beyond BPD: Backside Clock and Signal Routing for Sub-3nm (UT Austin, Intel)


A new technical paper titled "Beyond Backside Power: Backside Signal Routing as Technology Booster for Standard Cell Scaling" was published by researchers from University of Texas at Austin and Intel. Abstract "Advances in process technology enabling backside metals and contacts offer new Design-Technology Co-Optimization (DTCO) opportunities to further enhance power, performance, and area ... » read more

Statistical Model Checking As An Evaluation Tool of Microarchitectural Side Channels (Duke, Harvard, Univ. of Florida)


A new technical paper titled "Rigorous Evaluation of Microarchitectural Side-Channels with Statistical Model Checking" was published by researchers at Duke University, Harvard University and University of Florida. Abstract "Rigorous quantitative evaluation of microarchitectural side channels is challenging for two reasons. First, the processors, attacks, and defenses often exhibit probabili... » read more

Chip Industry Week in Review


The Open Compute Project (OCP) Summit kicked off this week in San Jose, dominated by open standards, massive scaling of AI infrastructure, chiplet architectures, and energy-efficiency. Among the highlights: An initiative to standardize data center infrastructure and advance Ethernet for AI. New contributions to OCP's Open Chiplet Economy ecosystem, including Arm's new Foundation Chiplet... » read more

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