Grouping Complex Wafer Defect Patterns Into Meaningful Clusters (Oregon State Univ., Micron)


A new technical paper titled "DECOR: Deep Embedding Clustering with Orientation Robustness" was published by researchers at Oregon State University and Micron Technology. Abstract "In semiconductor manufacturing, early detection of wafer defects is critical for product yield optimization. However, raw wafer data from wafer quality tests are often complex, unlabeled, imbalanced and can conta... » read more

Using AI/ML To Find And Correlate IC Test Data


What causes low yield in wafers? Usually it's due to design or process changes, but sometimes yield issues occur even if there haven't been any changes from one manufacturing lot to the next. Finding the cause requires some sleuthing, and the best approach for pinpointing problems is to mine design, process, and manufacturing data, and to correlate that data by date and time, by which equipment... » read more

EBook: Helping To Realize Chiplet Ambitions


The future of physical AI, from autonomous vehicles to robotics and aerospace, depends on overcoming the limitations of monolithic SoCs. As computing demands grow, a shift to scalable, modular, and reusable chiplet-based architectures is essential. This transition presents new challenges, from ensuring interoperability to managing complex system-level integration. How can you navigate this land... » read more

ONNX And Python To C++: State-Of-The-Art Graph Compilation


Nigel Drego, Co-founder and Chief Technology Officer at Quadric, presented the “ONNX and Python to C++: State-of-the-art Graph Compilation” tutorial at this year's Embedded Vision Summit. Quadric’s Chimera general-purpose neural processor executes complete AI/ML graphs—all layers, including pre- and post-processing functions traditionally run on separate DSP processors. Read more here. » read more

Frequency-Impedence Verification Of Power Delivery Network With HyperLynx PI For AMD Versal Adaptive SoC Devices


HyperLynx Decoupling analysis and the PDN Decoupling Optimizer are powerful tools for exploring various PDN structures and decoupling strategies. This paper presents a study showcasing the advantages of performing a HyperLynx decoupling analysis to verify PDN performance, and it highlights the extensive collaboration between Siemens and AMD in creating a complete system design flow for performi... » read more

Optimizing Optical Fiber Connections In Hyperscale Datacenters: A Simulation-Driven Approach


Hyperscale datacenters are redefining the limits of data transmission technology, driven by increasing demands for higher bandwidth, lower power consumption, and reduced latency. Through advanced simulation workflows and multiphysics integration, engineers can design, optimize, and validate optical coupling systems for next-generation datacenters. The use of Ansys Optics software for photonic c... » read more

Enabling The 448G Era: System Architecture And Standards For Next-Gen AI Networks


As Artificial Intelligence (AI) and Machine Learning (ML) workloads continue to reshape data center infrastructure, the need for higher bandwidth and lower latency has accelerated the need for a next-generation Ethernet. This white paper examines the industry’s shift toward 448G signaling—driven by scale-up and scale-out AI cluster demands—and outlines the evolving system architecture... » read more

Why Data-Over-Sound Is An Integral Part Of Any IoT Engineer’s Toolbox


Data-over-sound technology such as Chirp presents a compelling solution for many device-to-device connectivity applications, particularly for use cases that require frictionless, low cost connectivity with nearby devices. Download this white paper to: Understand the fundamental concepts and benefits of data-over-sound connectivity Explore the key application areas within the Internet... » read more

Microelectronics and Advanced Packaging Technologies Roadmap 2.0 (SRC)


The Semiconductor Research Corporation just released its Microelectronics and Advanced Packaging Technologies (MAPT) Roadmap 2.0, a comprehensive update to the industry’s first 3D semiconductor roadmap. The roadmap includes contributions of over 370 experts from 132 organizations, with updated content and a new chapter on digital twins and their applications. The roadmap was funded by the ... » read more

System-HW Co-Design Approach Combines Mono3D DRAM, NMP, and GPU Acceleration (UCSD, Georgia Tech, UIUC, Illinois Tech)


A new technical paper titled "Stratum: System-Hardware Co-Design with Tiered Monolithic 3D-Stackable DRAM for Efficient MoE Serving" was published by researchers at UC San Diego, Georgia Tech, University of Illinois Urbana-Champaign and Illinois Institute of Technology. Abstract "As Large Language Models (LLMs) continue to evolve, Mixture of Experts (MoE) architecture has emerged as a preva... » read more

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