The Week In Review: Design
By Jesse Allen - 20 Apr, 2018 - Comments: 0

M&A The ESD Alliance is merging with SEMI, becoming a SEMI Strategic Association Partner. SE Editor In Chief Ed Sperling argues that the merger has broad implications for the chip industry, particularly as smaller nodes require greater collaboration between design and manufacturing. Meanwhile, SEMI president and CEO Ajit Manocha explains why the combining will be of benefit to members of b... » read more

Mashup At 7nm
By Ed Sperling - 19 Apr, 2018 - Comments: 0

The merger of two standards organizations typically falls well below the radar of most engineers, but folding the ESD Alliance (formerly known as the EDA Consortium) into SEMI is a different kind of deal. Ever since the introduction of finFETs and multiple patterning, EDA tools have become an integral part of the development of new manufacturing processes. Without those tools, there is no po... » read more

Too Many, Too Few Rare Earths
By Mark LaPedus - 19 Apr, 2018 - Comments: 0

A team from Japan recently made a major discovery—they found massive deposits of rare earths on the ocean floor off the coast of Japan. The team of Waseda University, the University of Tokyo and the Japan Agency for Marine-Earth Science and Technology (JAMSTEC) found a deposit that equates to 16 million tons of rare earths. Rare earths are a group of critical materials used in various ele... » read more

Criticality of Wafer Edge Inspection and Metrology Data to All-Surface Defectivity Root Cause and Yield Analysis
By KLA - 19 Apr, 2018 - Comments: 0

Abstract As device sizes continue to increase on devices at 2x nm design rule and beyond and high wafer stress is worsening due to multi-film stacking in the vertical memory process, we observe an increasing trend in edge yield issues worldwide. Wafer edge inspection and metrology become thus critical to drive root cause analysis for improving the yield during a new technology ramp. Nowadays, ... » read more

Design Rule Complexity Rising
By Ed Sperling - 19 Apr, 2018 - Comments: 0

Variation, edge placement error, and a variety of other issues at new process geometries are forcing chipmakers and EDA vendors to confront a growing volume of increasingly complex, and sometimes interconnected design rules to ensure chips are manufacturable. The number of rules has increased to the point where it's impossible to manually keep track of all of them, and that has led to new pr... » read more

Toward A 5G, AI-Centric World
By Sundeep Bajikar - 19 Apr, 2018 - Comments: 0

The market environment over the coming years will continue to experience an explosion of data generation from a variety of new sources such as smart cars, smart factories, smart hospitals and smart network infrastructure. Data explosion combined with artificial intelligence (AI) will create a renaissance of computing and storage hardware. Mobile World Congress 2018 (MWC) reinforced this market ... » read more

New Patterning Options Emerging
By Mark LaPedus - 19 Apr, 2018 - Comments: 1

Several fab tool vendors are rolling out the next wave of self-aligned patterning technologies amid the shift toward new devices at 10/7nm and beyond. Applied Materials, Lam Research and TEL are developing self-aligned technologies based on a variety of new approaches. The latest approach involves self-aligned patterning techniques with multi-color material schemes, which are designed for us... » read more

Masks, Models And Alternative Lithography
By Jan Willis - 19 Apr, 2018 - Comments: 0

Every February an outstanding group of eBeam luminaries gathers at events hosted by the eBeam Initiative during the SPIE Advanced Lithography conference. It was our 10th annual lunch with standing room only attendance again this year. It’s an honor to get to know some of these very talented people. We started producing videos for the community over five years ago to share more of their storie... » read more

Modeling Semiconductor Process Variation
By Coventor - 19 Apr, 2018 - Comments: 0

3D semiconductors, 3D NAND Flash, FinFETS and other advanced devices are bringing tremendous opportunities to the semiconductor industry. Unfortunately, these devices are also bringing new design, process and production problems. Process variability has been a major contributor to production delays as feature sizes have decreased and process complexity has increased. Virtual fabrication is a co... » read more

Searching For EUV Defects
By Mark LaPedus - 19 Apr, 2018 - Comments: 1

Chipmakers hope to insert extreme ultraviolet (EUV) lithography at 7nm and/or 5nm, but several challenges need to be solved before this oft-delayed technology can be used in production. One lingering issue that is becoming more worrisome is how to find defects caused by [gettech id="31045" comment="EUV"] processes. These processes can cause random variations, also known as stochastic effects... » read more

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